Charge pump circuit with latch-up prevention
View Patent ↗In an embodiment of the invention, a charge pump circuit has a latch-up prevention circuit. The latch-up prevention circuit has a depletion P-channel MOS transistor and a resistor serially connected with each other between a negative output terminal and a ground terminal. A first bidirectional PNP-transistor is connected between a back gate of the depletion MOS transistor and the ground terminal. A second bidirectional PNP-transistor is connected between the back gate of the depletion MOS transistor and the negative output terminal. A third bidirectional PNP-transistor is between the ends of the resistor to bypass it. The base of the first bidirectional PNP-transistor is connected to the negative output terminal, the gate of the depletion MOS transistor and the bases of the second and third bidirectional PNP-transistors are connected to the ground terminal.
1. A charge pump circuit, integrated in a semiconductor substrate, generating a first output voltage and a second output voltage from an input voltage, a sign of the first output voltage being the same as the input voltage, a sign of the second output voltage being different from the input voltage, and absolute values of the output voltages are larger than the input voltage, the charge pump circuit comprising:
an output terminal of the second output voltage; and
a latch-up prevention circuit, embedded in the semiconductor substrate, including a depletion MOS transistor which connects the output terminal to a ground at startup of the charge pump circuit.
2. The charge pump circuit of claim 1 , wherein the latch-up prevention circuit further comprises:
a resistor serially connected with the depletion MOS transistor between the output terminal and the ground;
a first bidirectional bipolar transistor to connect a back gate of the depletion MOS transistor to the ground;
a second bidirectional bipolar transistor to connect the back gate of the depletion MOS transistor to the output terminal; and
a third bidirectional bipolar transistor to bypass the resistor.
3. The charge pump circuit of claim 2 , wherein the sign of the input voltage is positive and the sign of the second output voltage is negative,
the semiconductor substrate includes a P-substrate,
the voltage of the substrate includes the voltage of the output terminal,
the depletion MOS transistor includes a P-channel transistor and the bipolar transistors include PNP-transistors,
the depletion MOS transistor is connected between the output terminal and the resistor,
a base of the first bidirectional bipolar transistor is connected to the output terminal, and
a gate of the depletion MOS transistor and bases of the second and third bidirectional bipolar transistors are connected to the ground.
4. The charge pump circuit of claim 2 , wherein
the sign of the input voltage is negative and the sign of the second output voltage is positive,
the semiconductor substrate includes a N-substrate,
a voltage of a P-well on the substrate includes the voltage of the output terminal,
the depletion MOS transistor includes an N-channel transistor and the bipolar transistors include NPN-transistors,
the depletion MOS transistor is connected between the resistor and the ground,
a gate of the depletion MOS transistor and bases of the first and third bidirectional bipolar transistors are connected to the output terminal, and
a base of the second bidirectional bipolar transistor is connected to the ground.
5. A charge pump circuit generating an output voltage from an input voltage, comprising:
an input terminal receiving the input voltage;
an output terminal outputting the output voltage;
a voltage generating circuit generating and providing the output voltage to the output terminal, a sign of the output voltage being different from the input voltage and an absolute value of the output voltage being larger than the input voltage; and
a latch-up prevention circuit, embedded in a semiconductor substrate, which connects the output terminal to a ground on a condition that the output voltage of the output terminal reaches a predetermined voltage to prevent an increase of the output voltage of the output terminal and a thyristor operation of parasitic transistors,
wherein said latch-up prevention circuit includes:
a depletion MOS transistor which connects the output terminal to the ground at startup of the charge pump circuit.
6. The charge pump circuit of claim 5 , wherein the latch-up prevention circuit prevents the increase of the output voltage of the output terminal at startup of the charge pump circuit.
7. The charge pump circuit of claim 5 , wherein the depletion MOS transistor connects the output terminal to the ground according to a back gate voltage thereof which varies in accordance with the output voltage of the output terminal.
8. The charge pump circuit of claim 7 , wherein the latch-up prevention circuit further includes:
a resistor serially connected with the depletion MOS transistor between the output terminal and the ground.
9. The charge pump circuit of claim 8 , wherein the latch-up prevention circuit further includes:
a first bidirectional bipolar transistor to connect the back gate of the depletion MOS transistor to the ground and a second bidirectional bipolar transistor to connect a back gate of the depletion MOS transistor to the output terminal.
10. The charge pump circuit of claim 9 , wherein the latch-up prevention circuit further includes:
a third bidirectional bipolar transistor to bypass the resistor.
11. The charge pump circuit of claim 5 further comprising:
another voltage generating circuit generating and providing another output voltage to another output terminal, a sign of the another output voltage being the same as the input voltage and an absolute value of the another output voltage being larger than the input voltage.
12. The charge pump circuit of claim 5 , wherein the latch-up prevention circuit further comprises:
a first bidirectional bipolar transistor to connect a back gate of the depletion MOS transistor to the ground;
a second bidirectional bipolar transistor to connect the back gate of the depletion MOS transistor to the output terminal; and
a third bidirectional bipolar transistor to bypass a resistor coupled in series with the depletion MOS transistor.
13. The charge pump circuit of claim 12 , wherein
the semiconductor substrate includes a P-substrate,
the voltage of the substrate includes the voltage of the output terminal, and
the depletion MOS transistor includes a P-channel transistor and the bipolar transistors include PNP-transistors.
14. The charge pump circuit of claim 13 , wherein
the depletion MOS transistor is connected between the output terminal and the resistor,
a base of the first bidirectional bipolar transistor is connected to the output terminal, and
a gate of the depletion MOS transistor and bases of the second and third bidirectional bipolar transistors are connected to the ground.
15. The charge pump circuit of claim 12 , wherein
the sign of the input voltage is negative and the sign of the second output voltage is positive,
the semiconductor substrate includes an N-substrate,
a voltage of a P-well on the substrate includes the voltage of the output terminal,
the depletion MOS transistor includes an N-channel transistor and the bipolar transistors include NPN-transistors,
the depletion MOS transistor is connected between the resistor and the ground,
a gate of the depletion MOS transistor and bases of the first and third bidirectional
bipolar transistors are connected to the output terminal, and
a base of the second bidirectional bipolar transistor is connected to the ground.
16. A charge pump circuit generating an output voltage from an input voltage, comprising:
an input terminal receiving the input voltage;
an output terminal outputting the output voltage;
a voltage generating circuit generating and providing the output voltage to the output terminal, a sign of the output voltage being different from the input voltage and an absolute value of the output voltage being larger than the input voltage; and
a latch-up prevention circuit, embedded in a semiconductor substrate, which connects the output terminal to a ground on a condition that the output voltage of the output terminal reaches a predetermined voltage to prevent an increase of the output voltage of the output terminal and a thyristor operation of parasitic transistors,
wherein the latch-up prevention circuit includes:
a depletion MOS transistor to connect the output terminal to the ground in accordance with the output voltage of the output terminal.