Semiconductor device having a trench surrounding each of plural unit cells
View Patent ↗A semiconductor device comprises a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET). The unit cell includes a first source region formed in a first base region, a second source region formed in the first base region and separated from the first source region, and a second base region formed in the first base region and disposed between the first and second source regions. The semiconductor device further comprises a trench gate formed in a vicinity of each of the plurality of unit cells. The second base region of an unit cell is separated from the second base region of an adjacent unit cell, and the first or second source region of an unit cell is separated from the first or second source region of an adjacent unit cell.
1. A semiconductor device comprising:
a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET), including:
a first source region formed in a first base region,
a second source region formed in the first base region and separated from the first source region, and
a second base region formed in the first base region and disposed between the first and second source regions, said second base region having a higher impurity concentration than said first base region; and
a trench gate surrounding on all sides each of the plurality of unit cells, so that each of the first and second source regions and the second base region are in direct contact with the trench gate.
2. The semiconductor device according to claim 1 , wherein the first source region, the second source region, and the second base region are each rectangular-shaped.
3. A semiconductor device comprising;
a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET), including:
a first source region formed in a first base region,
a second source region formed in the first base region and separate and distinct from the first source region, and
a second base region formed in the first base region and disposed between the first and second source regions, said second base region having a higher impurity concentration than said first base region; and
a trench gate surrounding on all sides each of the plurality of unit cells,
wherein a channel region in the first base region under the first and second source regions is formed along a side surface of each unit cell except for a part adjacent to the second base region.
4. The semiconductor device according to claim 3 , wherein the first source region, the second source region, and the second base region are each rectangular-shaped, and the channel region in each unit cell is substantially U-shaped.
5. The semiconductor device according to claim 1 , wherein the first source region, the second source region, and the second base region of the unit cells are arranged in a same first direction.
6. The semiconductor device according to claim 3 , wherein the first source region, the second source region, and the second base region of the unit cells are arranged in a same first direction.
7. The semiconductor device according to claim 5 , wherein positions of the second base regions of adjacent unit cells are offset from each other in the first direction or a second direction perpendicular to the first direction.
8. The semiconductor device according to claim 6 , wherein positions of the second base regions of adjacent unit cells are offset from each other in the first direction or a second direction perpendicular to the first direction.
9. The semiconductor device according to claim 7 , wherein an offset distance is one-half of a length of one unit cell in the first direction.
10. The semiconductor device according to claim 8 , wherein an offset distance is one-half of a length of one unit cell in the first direction.
11. The semiconductor device according to claim 1 , wherein the unit cells are arranged in such a way that a gap between the unit cells is T-shaped.
12. The semiconductor device according to claim 3 , wherein the unit cells are disposed in such a way that a gap between the unit cells is T-shaped.
13. A semiconductor device comprising:
a plurality of unit cells, each comprising a vertical metal oxide semiconductor field effect transistor (MOSFET), including:
a first source region formed vertically above a first base region,
a second source region formed vertically above the first base region and separated from the first source region, and
a second base region formed in the first base region and disposed between the first and second source regions, said second base region having an impurity concentration higher than said first base region, bottom surfaces of said first and second base regions are coplanar; and
a trench gate formed between adjacent ones of the plurality of unit cells,
wherein one of the first and second source regions of a unit cell extends over an entirety of said first base region between said second base region and said trench gate.
14. The semiconductor device according to claim 1 , wherein some unit cells of the plurality of unit cells further comprise an impurity diffusion region having substantially the same size as the plurality of unit cells that comprise the vertical MOSFET.