Processor having content addressable memory with command ordering

1. A method of ordering memory commands, comprising:

placing a portion of a received command for a first memory address into a first location of a content addressable memory (CAM) comprising an address field to store the first memory address, a first field, a second field and a command field to store the portion of the received command in a linked list structure;

placing a first command for an address not contained in the CAM in a corresponding command queue;

placing the portion of the received command in a coherency command queue configured to store commands waiting for related commands to be completed, the commands stored in the coherency command queue have addresses contained in the CAM;

placing a second command for the first memory address in a command field of a second location of the CAM;

updating the first field of the first CAM location to point to the second CAM location; and

updating the second field of the first CAM location to point to the second CAM location.

2. The method according to claim 1 , further comprising:

placing a third command for the first memory address in a third location of the CAM;

updating the second field of the first CAM location to point to the third CAM location; and

updating the first field of the second CAM location to point to the third CAM location.

3. The method according to claim 1 , wherein the received command is a read/modify/write (RMW) command, and

placing the portion of the received command in a coherency command queue comprises placing a write command of the RMW command in the coherency command queue.

4. The method according to claim 3 , further comprising waiting for a read command of the RMW command to complete before performing the write command of the RMW command stored in the coherency command queue.

5. The method according to claim 1 wherein placing a first command for an address not contained in the CAM in a corresponding command queue comprises placing a read command into a read command queue if the read command is for an address not contained in the CAM.

6. The method according to claim 1 wherein placing a first command for an address not contained in the CAM in a corresponding command queue comprises placing a write command into a write command queue if the write command is for an address not contained in the CAM.

7. The method according to claim 1 , further including setting a flag for a first unprocessed command in the linked list of commands in the CAM.

8. The method according to claim 1 , further including storing data associated with the received command in a data storage field of the CAM.

9. An article comprising:

a storage medium having stored thereon instructions executed by a machine, the instructions comprising instructions causing the machine to:

place a portion of a received command for a first memory address into a first location of a content addressable memory (CAM) comprising an address field to store the first memory address, a first field, a second field and a command field to store the portion of a received command in a linked list structure;

place a first command for an address not contained in the CAM in a corresponding command queue;

place the portion of the received command in a coherency command queue configured to store commands, waiting for related commands to be completed, the commands stored in the coherency command queue have addresses contained in the CAM;

place a second command for the first memory address in a command field of a second location of the CAM;

update the first field of the first CAM location to point to the second CAM location; and

update the second field of the first CAM location to point to the second CAM location.

10. The article according to claim 9 , further comprising instructions causing a machine to:

place a third command for the first memory address in a third location of the CAM;

update the second field of the first CAM location to point to the third CAM location; and

update the first field of the second CAM location to point to the third CAM location.

11. The article according to claim 9 , wherein the portion of the received command is a read/modify/write (RMW) command, and

wherein instructions causing a machine to place the portion of the received command in a coherency command queue comprise instructions causing a machine to place a write command of the RMW command in a coherency command queue.

12. The article according to claim 11 further comprising instructions causing a machine to wait for a read command of the RMW command to complete before performing the write command of the RMW command stored in the coherency command queue.

13. The article according to claim 9 wherein instructions causing a machine to place a first command for an address not contained in the CAM in a corresponding command queue comprises instructions causing a machine to place a read command into a read command queue if the read command is for an address not contained in the CAM.

14. The article according to claim 9 , further including instructions to enable storing data associated with the received command in a data storage field of the CAM.

15. The article according to claim 9 wherein instructions causing a machine to place a command for an address not contained in the CAM in a corresponding command queue comprises instructions causing a machine to place a write command into a write command queue if the write command is for an address not contained in the CAM.

16. A processing unit, comprising:

a main command memory to store received memory commands;

a content addressable memory (CAM) including

an address field to store an address of a command;

a first field to point to a next command to be processed in a linked list of commands to be executed;

a second field to point to a last command in the linked list; and

a command field to store the command,

a read command memory configured to store a read command if the read command is for an address not contained in the CAM;

a write command memory configured to store a write command if the write command is for an address not contained in the CAM; and

a coherency command queue configured to store commands waiting for related commands to be completed, the commands stored in the coherency command queue have addresses contained in the CAM.

17. The processing unit according to claim 16 , wherein the CAM further includes a data store field.

18. A network forwarding device, comprising:

at least one line card to forward data to ports of a switching fabric;

the at least one line card including a network processor having multi-threaded microengines configured to execute microcode resulting in the following:

placing a portion of a received command for a first memory address into a first location of a content addressable memory (CAM) comprising an address field to store the first memory address, a first field, a second field and a command field to store the portion of the received command in a linked list structure;

placing a first command for an address not contained in the CAM in a corresponding command queue;

placing the portion of the received command in a coherency command queue configured to store commands waiting for related commands to be completed, the commands stored in the coherency command queue have addresses contained in the CAM;

placing a second command for the first memory address in a command field of a second location of the CAM;

updating the first field of the first CAM location to point to the second CAM location; and

updating the second field of the first CAM location to point to the second CAM location.

19. The device according to claim 18 , further comprising:

placing a third command for the first memory address in a third location of the CAM;

update the second field of the first CAM location to point to the third CAM location; and

update the first field of the second CAM location to point to the third CAM location.

20. The device according to claim 18 , wherein the received command is a read/modify/write (RMW) command, and further including

wherein placing the portion of the received command in a coherency command queue configured to store commands, having addresses contained in the CAM, waiting for related commands to be completed comprises placing a write command of the RMW command in the coherency command queue.

21. The device according to claim 20 , further including waiting for a read command of the RMW command to complete before performing the write for the RMW command.

22. The device according to claim 18 wherein placing a first command for an address not contained in the CAM in a corresponding command queue comprises placing a read command into a read command queue if the read command is for an address not contained in the CAM.

23. The device according to claim 18 , further including storing data associated with the received command in a data storage field of the CAM.

24. A content addressable memory (CAM) structure comprising:

fields, the fields comprising:

a command field to store a portion of a received command; and

an address field to store a memory address,

wherein at least a portion of the fields are used in a linked list structure for links and a link includes CAM entries having an identical memory address stored in the address field,

wherein the CAM is connected to a read command memory, a write command memory and a coherency command memory,

wherein the command memory is configured to store commands waiting for related commands to be completed, the commands stored in the coherency command queue have addresses contained in the CAM;

wherein the read command memory is configured to store a read command if the read command is for an address not contained in the CAM and the write command memory is configured to store a write command if the write command is for an address not contained in the CAM.

25. The CAM structure of claim 24 wherein the fields further comprise:

a first pointer field to point to a next CAM entry in the link; and

a second pointer field to point to a last CAM entry in the link.