Metal interconnection structure of semiconductor device and method of forming the same
View Patent ↗Provided is a metal interconnection structure of a semiconductor device, having: a lower metal layer disposed on an insulating layer formed on a semiconductor device; a contact plug disposed on the lower metal layer; a supporting layer disposed to surround the contact plug; an upper metal layer disposed on the contact plug and the supporting layer; and an air layer interposed between the lower and upper metal layers to insulate the lower metal layer from the upper metal layer.
1. A method of forming a metal interconnection structure of a semiconductor device, comprising steps of:
forming a lower metal layer on an interlayer insulating layer formed on a semiconductor substrate;
forming a first organic layer to cover the interlayer insulating layer and the lower metal layer;
forming a supporting layer on the first organic layer;
forming a hole therethrough to expose a portion of a surface of the first organic layer in the supporting layer by selectively removing a portion of the supporting layer;
forming a second organic layer on the supporting layer and the first organic layer;
forming an etching stopper layer on the second organic layer;
forming a mask layer pattern on the etching stopper layer, the mask layer pattern having an opening for exposing a portion of a surface of the etching stopper layer;
performing an etching process by using the mask layer pattern as an etching mask to remove a portion of the etching stopper layer exposed through the etching mask;
forming a trench in the second organic layer and a via hole in the first organic layer by removing a portion of the second organic layer that is exposed so as to expose a portion of the first organic layer through the hole formed by a step of forming a hole through the supporting layer and subsequently removing the portion of the first organic layer that is exposed through the hole;
forming a metal layer to fill the trench and via hole;
forming a contact plug filling the via hole and an upper metal layer filling the trench by performing a planarization process until a surface of the etching stopper layer is exposed; exposing the second organic layer by removing the etching stopper layer; and sequentially removing the first and second organic layers.
2. The method of claim 1 , wherein the first and second organic layers are photoresist layers.
3. The method of claim 2 , wherein the step of sequentially removing the first and second organic layers is performed by a plasma process.
4. The method of claim 1 , wherein the supporting layer is a nitride layer.
5. The method of claim 1 , wherein the etching stopper layer is a nitride layer.
6. A method of forming a metal interconnection structure of a semiconductor device, comprising steps for:
forming a lower metal layer on an interlayer insulating layer formed on a semiconductor substrate;
forming a first organic layer to cover the interlayer insulating layer and the lower metal layer;
forming a supporting layer on the first organic layer;
forming a hole therethrough to expose a portion of a surface of the first organic layer in the supporting layer by selectively removing a portion of the supporting layer;
forming a second organic layer on the supporting layer and the first organic layer;
forming an etching stopper layer on the second organic layer;
forming a mask layer pattern on the etching stopper layer, the mask layer pattern having an opening for exposing a portion of a surface of the etching stopper layer;
performing an etching process by using the mask layer pattern as an etching mask to remove a portion of the etching stopper layer exposed through the etching mask;
forming a trench in the second organic layer and a via hole in the first organic layer by removing a portion of the second organic layer that is exposed so as to expose a portion of the first organic layer through the hole formed by the step for forming a hole through the supporting layer and subsequently removing the portion of the first organic layer that is exposed through the hole;
forming a metal layer to fill the trench and via hole;
forming a contact plug filling the via hole and an upper metal layer filling the trench by performing a planarization process until a surface of the etching stopper layer is exposed; exposing the second organic layer by removing the etching stopper layer; and sequentially removing the first and second organic layers.