Non-volatile memory device and fabricating method thereof
View Patent ↗The present invention provides a non-volatile memory device and fabricating method thereof, by which a cell size can be lowered despite high degree of cell integration and by which the device fabrication is facilitated. The present invention includes at least two trench isolation layers arranged in a device isolation area of a semiconductor substrate, each having a first depth, a first conductive type well arranged between the at least two trench isolation layers to have a second depth smaller than the first depth, a second conductive type source region and a second conductive type drain region arranged in a prescribed upper part of the first conductive type well to be separated from each other by a channel region in-between, an ONO layer on the channel region of the semiconductor substrate, the ONO layer comprising a lower oxide layer, a nitride layer, and an upper oxide layer, and a wordline conductor layer on the ONO layer.
1. A method of fabricating a non-volatile memory device, comprising the steps of:
forming at least two trench isolation layers having a first depth each in a device isolation area of a semiconductor substrate, wherein the trench isolation layers comprise sidewalls having vertical profiles;
forming a first conductive type well having a second depth smaller than the first depth in an active area of the semiconductor substrate defined by the at least two trench isolation layers, wherein a width of a lower part of the first conductive the well is equal to that of an upper part of the first conductive type well;
forming an ONO layer on a prescribed upper area of the first conductive type well wherein the ONO layer comprises a lower oxide layer, a nitride layer, and an upper oxide layer;
forming a wordline conductor layer on the ONO layer; and
forming source and drain regions in the prescribed upper area of the first conductive type well.
2. The method of claim 1 , wherein the first depth of the first trench isolation layer is equal to or greater than 5,000 Å.
3. The method of claim 2 , wherein the first depth of the trench isolation layer is equal to or greater than 8,000 Å and the second depth of the first conductive type well is 6,000 Å.
4. The method of claim 1 , wherein the lower oxide layer is a tunnel oxide layer, the nitride layer is a charge trap layer, and the upper oxide layer is an insulating layer.
5. The method of claim 4 , wherein the tunnel oxide layer is formed about 10˜50Å thick, the nitride layer is formed about 50˜60 Å thick, and the insulating layer is formed about maximum 80 Å thick.
6. The method of claim 4 , wherein the tunnel oxide layer and the nitride layer are formed by thermal oxidation and chemical vapor deposition, respectively.
7. A method of fabricating a non-volatile memory device, comprising the steps of:
forming at least two trench isolation layers having a first depth each in a device isolation area of a semiconductor substrate, wherein the trench isolation layers comprise sidewalls having vertical profiles, the sidewalls being perpendicular to the substrate;
forming a first conductive type well having a second depth smaller than the first depth in an active area of the semiconductor substrate defined by the at least two trench isolation layers;
forming an ONO layer on a prescribed upper area of the first conductive type well wherein the ONO layer comprises a lower oxide layer, a nitride layer, and an upper oxide layer;
forming a wordline conductor layer on the ONO layer; and
forming source and drain regions in the prescribed upper area of the first conductive type well.