Method of fabricating flash memory device
View Patent ↗The present invention provides a method of fabricating a flash memory device, in which floating gates in neighbor cells are separated from each other without using photolithography, which enhances electrical characteristics of the device, and which facilitates a cell size reduction. The present invention includes forming a mask defining a trench forming area on a semiconductor substrate, forming a trench in the semiconductor layer by removing a portion of the semiconductor layer using the mask, forming a device isolation layer filling up the trench to maintain an effective isolation layer thickness exceeding a predefined thickness, removing the mask, forming a conductor layer over the substrate including the device isolation layer, planarizing the conductor layer and the device isolation layer to lie in a same plane, and forming an insulating layer over the substrate including the conductor patterns.
1. A method of fabricating a flash memory device, comprising the steps of:
forming a mask defining a trench-forming area on a semiconductor substrate;
forming a trench in the substrate by removing a portion of the substrate using the mask;
forming a device isolation layer by filling the trench to maintain an effective isolation layer thickness exceeding a predetermined thickness;
removing the mask;
forming a conductor layer over the substrate and the device isolation layer;
partially removing the conductor layer and the device isolation layer to planarize the conductor layer and the device isolation layer;
partially removing the planarized device isolation layer to reduce the effective isolation layer thickness; and
forming an insulating layer over the conductor layer and the partially removed planarized device isolation layer.
2. The method of claim 1 , wherein the mask is a nitride layer pattern.
3. The method of claim 2 , wherein the nitride layer pattern is formed to have a thickness of about 1,500˜4,500 Å.
4. The method of claim 1 , wherein the effective isolation layer thickness is at least 1,000 Å.
5. The method of claim 1 , wherein planarization of the conductor layer and the device isolation layer is carried out by chemical mechanical polishing.