Trench isolation method in flash memory device
View Patent ↗The present invention provides a trench isolation method in a flash memory device, by which stability and reliability of the device are enhanced in a manner of forming a pad oxide layer thick in the vicinity of an edge of a trench isolation layer. The present invention includes forming a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon, forming a trench in the semiconductor substrate corresponding to the device isolation area, removing an exposed portion of the first insulating layer pattern enough to expose a portion of the semiconductor substrate in the active area adjacent to the trench, forming a sidewall oxide layer on an inside of the trench and the exposed portion of the semiconductor substrate, filling up the trench with a third insulating layer to cover the sidewall oxide layer, and removing the mask layer pattern.
1. A trench isolation method in a flash memory device, comprising the steps of:
forming a mask layer pattern on a mask layer pattern on a semiconductor substrate to expose a device isolation area but to cover an active area thereof, the mask layer pattern comprising a first insulating layer pattern and a second insulating layer pattern stacked thereon;
forming a trench in the semiconductor substrate corresponding to the device isolation area;
removing an exposed portion of the insulating layer pattern enough to expose a first portion of the semiconductor substrate in the active area adjacent to the trench;
forming a sidewall oxide layer on an inside of the trench and the first exposed portion of the semiconductor substrate;
filling up a trench with a third insulation layer to cover the sidewall oxide layer;
removing the mask layer pattern to expose a second portion of the semiconductor substrate; and
forming a tunnel oxide layer on the exposed second portion of the semiconductor substrate by laterally removing a portion of the first insulation layer to have a thickness less than a thickness of the sidewall oxide layer.
2. The trench isolation method of claim 1 , wherein the first and second insulating layer patterns are formed of nitride and TEOS oxide, respectively.
3. The trench isolation method of claim 2 , wherein the exposed portion of the first insulating layer pattern is removed by wet etch using H 3 PO 4 .
4. The trench isolation method of claim 1 , wherein the exposed portion of the first insulating layer pattern is laterally removed to a thickness of 30˜150 Å.
5. The trench isolation method of claim 1 , wherein the sidewall oxide layer is formed 100˜300 Å thick.
6. The trench isolation method of claim 1 , wherein the third insulating layer is formed of high density plasma oxide.
7. The trench isolation method of claim 1 , wherein removing the mask layer pattern comprises the steps of:
planarizing the third insulating layer until a topside of the first insulating layer pattern is exposed; and
removing the first insulating layer pattern.
8. The trench isolation method of claim 7 , wherein the first insulating layer pattern is removed by wet etch.