Non-volatile memory device and fabricating method thereof
View Patent ↗The present invention provides a non-volatile memory device and fabricating method thereof, in which a height of a floating gate conductor layer pattern is sustained without lowering a degree of integration and by which a coupling ratio is raised. The present invention includes a trench type device isolation layer defining an active area within a semiconductor substrate, a recess in an upper part of the device isolation layer to have a prescribed depth, a tunnel oxide layer on the active area of the semiconductor substrate, a floating gate conductor layer pattern on the tunnel oxide layer, a conductive floating spacer layer provided to a sidewall of the floating gate conductor layer pattern and a sidewall of the recess, a gate-to-gate insulating layer on the floating fate conductor layer pattern and the conductive floating spacer layer, and a control gate conductor layer on the gate-to-gate insulating layer.
1. A method of fabricating a non-volatile memory device, comprising the steps of:
forming a trench type device isolation layer defining an active area within a semiconductor substrate;
forming a tunnel oxide layer only on the active area of the semiconductor substrate;
forming a floating gate conductor layer on the tunnel oxide layer and the device isolation layer;
forming a floating gate conductor layer pattern exposing a portion of the device isolation layer by patterning the floating gate conductor layer;
forming a recess in an upper part of the device isolation layer by removing the exposed portion of the device isolation layer;
forming a conductive floating spacer layer on a sidewall of the floating gate conductor layer pattern and a sidewall of the recess of the device isolation layer;
anisotropic etching the conductive floating spacer layer to expose an upper conductive surface of the floating gate conductor layer pattern;
forming a gate-to-gate insulating layer on the floating gate conductor layer pattern and the conductive floating spacer layer; and
forming a control gate conductor layer on the gate-to-gate insulating layer.
2. The method of claim 1 , wherein the floating gate conductor layer pattern and the recess of the device isolation layer are formed by one etch process using a same mask layer pattern as an etch mask.
3. The method of claim 1 , the conductive floating spacer layer forming step comprising the steps of:
forming a floating space conductor layer on the sidewalls of the floating gate conductor layer pattern and the recess of the device isolation layer; and
anisotropically etching the floating spacer conductor layer to expose an upper surface of the floating gate conductor layer pattern.
4. The method of claim 3 , wherein the floating spacer conductor layer is anisotropically etched by etchback.
5. The method of claim 1 , wherein the gate-to-gate insulating layer comprises an oxide/nitride/oxide stacked layer.
6. The method of claim 1 , wherein the depth of the recess is between approximately 300 Å and approximately 2,000 Å.