Organic light emitting display with circuit measuring pad and method of fabricating the same
View Patent ↗An organic light emitting display and method of fabricating the same are disclosed. The light emitting display includes: a substrate having a display region and a circuit measuring pad region; source and drain electrodes arranged above the display region and a first conductive layer arranged above the circuit measuring pad region on the same layer as the source and drain electrodes; a first insulating layer on the source and drain electrodes and the first conductive layer; first and second via holes formed in the first insulating layer, the first via hole exposing the source or drain electrode, the second via hole exposing the first conductive layer; a pixel electrode contacting the source or drain electrode through the first via hole, and a second conductive layer contacting the first conductive layer through the second via hole; and a pixel defining layer which exposes the pixel electrode and formed on the second conductive layer.
1. An organic light emitting display comprising:
a substrate having a display region and a circuit measuring pad region;
source and drain electrodes arranged above the display region, and a first conductive layer arranged above the circuit measuring pad region on the same layer as the source and drain electrodes;
a first insulating layer arranged on the source and drain electrodes and the first conductive layer;
first and second via holes formed in the first insulating layer, the first via hole exposing the source or drain electrode, the second via hole exposing the first conductive layer;
a pixel electrode contacting the source or drain electrode through the first via hole, and a second conductive layer contacting the first conductive layer through the second via hole; and
a pixel defining layer which exposes the pixel electrode and formed on the second conductive layer.
2. The display of claim 1 , wherein the second conductive layer has a thickness in a range of 100 to 1,000 Å.
3. The display of claim 1 , wherein the pixel defining layer has a thickness of 3,000 Å or less.
4. The display of claim 1 , wherein the second via hole has a taper angle of 50° or less.
5. The display of claim 1 , wherein an edge of the first conducive layer has a taper angle of 50° or less.
6. The display of claim 1 , wherein the first insulating layer is a passivation layer.
7. The display of claim 6 , wherein the first insulating layer further includes a planarization layer arranged on the passivation layer.
8. The display of claim 7 , wherein the second via hole has a taper angle of 50° or less.
9. The display of claim 7 , wherein the planarization layer includes an opening which exposes the circuit measuring pad region, and the second via hole is arranged in the passivation layer.