Method for fabricating vertical transistor
View Patent ↗A method for fabricating a vertical transistor including forming a first junction area in a semiconductor substrate, forming a polysilicon layer by using an epitaxial growth in the substrate, forming a second junction area in the polysilicon layer, and forming a plug junction area in the polysilicon layer, the plug junction area electrically connected with the first junction area. The method also includes forming a trench by selectively etching and removing the polysilicon layer to expose the first junction area, sequentially depositing a gate insulating layer and a conductive layer for a first gate electrode on the trench and the polysilicon layer, and forming the first gate electrode by selectively patterning the conductive layer. The method further includes forming an insulating interlayer on an entire surface of the substrate including the first gate electrode, forming via-holes for exposing predetermined portions of the first junction area, the first gate electrode, and the plug junction area, and forming source/drain electrodes and a second gate electrode respectively connected with the first junction area, the first gate electrode, and the plug junction area by forming a metal layer within the via-holes.
1. A method for fabricating a vertical transistor comprising:
forming a first junction area in a semiconductor substrate;
forming a polysilicon layer on an epitaxial layer in the substrate;
forming a second junction area in the polysilicon layer;
forming a plug junction area in the polysilicon layer, the plug junction area electrically connected with the first junction area;
forming a trench by selectively etching and removing the polysilicon layer to expose the first junction area;
sequentially depositing a gate insulating layer and a conductive layer for a first gate electrode on the trench and the polysilicon layer;
forming the first gate electrode by selectively patterning the conductive layer;
forming an insulating interlayer on an entire surface of the substrate including the first gate electrode;
forming via-holes for exposing predetermined portions of the first junction area, the first gate electrode, and the plug junction area; and
forming source/drain electrodes and a second gate electrode respectively connected with the first junction area, the first gate electrode, and the plug junction area by forming a metal layer within the via-holes.
2. The method of claim 1 , wherein the steps of forming the first and second junction areas and the plug junction area include implanting ions at an energy between about 5 keV and about 50 keV and a density between about 1×10 15 and about 5×10 15 ions/cm 2 .
3. The method of claim 1 , wherein the step of forming the polysilicon layer includes forming the polysilicon layer with a thickness between about 0.5 μm and about 3 μm.
4. A method for fabricating a vertical transistor comprising:
a step for forming a first junction area in a semiconductor substrate;
a step for forming a polysilicon layer on an epitaxial layer in the substrate;
a step for forming a second junction area in the polysilicon layer;
a step for forming a plug junction area in the polysilicon layer, the plug junction area electrically connected with the first junction area;
a step for forming a trench by selectively etching and removing the polysilicon layer to expose the first junction area;
a step for sequentially depositing a gate insulating layer and a conductive layer for a first gate electrode on the trench and the polysilicon layer;
a step for forming the first gate electrode by selectively patterning the conductive layer;
a step for forming an insulating interlayer on an entire surface of the substrate including the first gate electrode;
a step for forming via-holes for exposing predetermined portions of the first junction area, the first gate electrode, and the plug junction area; and
a step for forming source/drain electrodes and a second gate electrode respectively connected with the first junction area, the first gate electrode, and the plug junction area by forming a metal layer within the via-holes.
5. The method of claim 4 , wherein the steps for forming the first and second junction areas and the plug junction area include steps for implanting ions at an energy between about 5 keV and about 50 keV and a density between about 1×10 15 and about 5×10 15 ions/cm 2 .
6. The method of claim 4 , wherein the step for forming the polysilicon layer includes a step for forming the polysilicon layer with a thickness between about 0.5 μm and about 3 μm.