IP Library Granted Patent US 7,537,864
Granted Patent B2
US 7,537,864 · App. 11/020,131 · Granted May 26, 2009

Hole pattern design method and photomask

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Quick Facts
Patent No.
US 7,537,864
App. No.
11/020,131
Granted
May 26, 2009
Kind
B2
Abstract

A method of designing hole patterns for arranging hole patterns on a pattern drawing of a photomask used during an exposure process in semiconductor integrated circuit manufacturing, wherein a grid is provided on the pattern drawing with a space smaller than a minimum pitch allowed by the design rule of the semiconductor integrated circuit, and the hole patterns are provided at lattice points, which are the intersections of the grid. Flexibility of hole pattern arrangement is improved and the quality of hole pattern arrangement can be easily evaluated.

Claims (16)

1. A method of designing hole patterns for arranging hole patterns on a pattern drawing of a photomask used during an exposure process in semiconductor integrated circuit manufacturing,

the method comprising:

providing a grid on a pattern drawing with a space smaller than a minimum pitch allowed by a design rule of said semiconductor integrated circuit, and

providing said hole patterns at lattice points, which are the intersections of said grid.

2. The method of designing hole patterns as defined in claim 1 wherein the space of said grid is half of said minimum pitch.

3. The method of designing hole patterns as defined in claim 1 wherein auxiliary patterns, which are patterns not transferred onto a photoresist layer during said exposure process, are provided at lattice points located at a distance not less than said minimum pitch from a gravity center in each of said hole patterns, excluding the lattice points at which said hole patterns are provided.

4. The method of designing hole patterns as defined in claim 3 wherein the space of said grid is half of said minimum pitch.

5. A photomask onto which said hole patterns and said auxiliary patterns arranged by a method of designing hole patterns as defined in claim 3 are transferred.

6. A method of designing hole patterns for arranging hole patterns and auxiliary patterns on a pattern drawing of a photomask used during an exposure process in semiconductor integrated circuit manufacturing,

the method comprising:

providing hole patterns on a pattern drawing of a photomask, and providing auxiliary patterns on said pattern drawing,

wherein said auxiliary patterns are not transferred onto a photoresist layer during an exposure process, and said hole patterns and said auxiliary patterns are arranged so that a side of a similar pattern which is obtained by enlarging each of said hole patterns and said auxiliary patterns by a prescribed multiplier, centering its gravity center so that each pattern overlaps with other similar patterns.

7. A method of designing hole patterns as defined in claim 6 wherein the value of said multiplier is 3.

8. A photomask onto which said hole patterns and said auxiliary patterns arranged by a method of designing hole patterns as defined in claim 6 are transferred.

9. A method of designing hole patterns for arranging hole patterns and auxiliary patterns on a pattern drawing of a photomask used during an exposure process in semiconductor integrated circuit manufacturing wherein the pattern of said auxiliary patterns are not transferred onto a photoresist layer during said exposure process, and said hole patterns and said auxiliary patterns are arranged so that when a unit graphic is a square whose side is three times as long as the densest pitch, which is the minimum value of the distance between gravity centers, one in each of said hole patterns, and when said auxiliary patterns are replaced by said hole patterns, the area of hole patterns within said unit graphic placed at an optional position on said pattern drawing is 60% or larger of the area of the maximum number of said hole patterns that can be arranged within said unit graphic.

10. A photomask onto which said hole patterns and said auxiliary patterns arranged by a method of designing hole patterns as defined in claim 9 are transferred.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Nov 11, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025346/0975 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2004
From: FUJIMOTO, MASASHI; MATSUURA, SEIJI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 016138/0185 →