Semiconductor device and fabrication method thereof
View Patent ↗A bonding pad of a semiconductor device and a fabrication method thereof are disclosed. A semiconductor device having a pad formed by exposing a predetermined region of a metal line formed over a semiconductor substrate includes an alloy layer formed on the metal line exposed through the pad. The alloy layer is formed from a reaction between the metal line and a metal having a melting point less than or equal to 1000° C.
1. A method of fabricating a semiconductor device comprising:
forming a via having substantially vertical sidewalls by etching a predetermined region of an insulating layer to expose a semiconductor substrate;
filling the via with a metal to form an outermost metal line;
forming a reaction layer on the outermost metal line and the insulating layer, wherein the reaction layer has a melting point of less than or equal to 1000° C.;
performing a heat treatment process to react the reaction layer and the outermost metal line, thereby forming an alloy layer on a interface between the reaction layer and the outermost metal line; and
removing an unreacted portion of the reaction layer and a first portion of the alloy layer to expose the insulating layer, such that a second portion of the alloy layer remains within the via.
2. The method of claim 1 , wherein forming the reaction layer comprising a physical vapor deposition process including a sputtering method performed at a temperature of 300° C. or less.
3. The method of claim 1 , wherein the heat treatment process comprises exposure to a temperature of 350 to 450° C. for a duration of 10 to 60 minutes.
4. The method of claim 1 , wherein the insulation layer comprises an oxide layer.
5. The method at claim 1 , further comprising an exposed metal line in the exposed semiconductor substrate.
6. The method of claim 1 , wherein the reaction layer comprises a material selected from the group consisting of aluminum, lead, and silver.
7. The method of claim 6 , wherein forming the reaction layer comprises depositing the selected material to a thickness that is less than a thickness of the outermost metal line.
8. The method of claim 1 , wherein the outermost metal line is comprises copper.
9. The method of claim 8 , further comprising forming a barrier metal layer in the via prior to forming the outermost metal line.
10. The method of claim 9 , wherein the barrier metal layer comprises a metal selected from the group consisting of Ti, Ta, TiN, and TaN.
11. The method of claim 9 , wherein the barrier metal layer is formed to a thickness between 200 and 800Å.
12. The method of claim 9 , wherein the barrier metal covers all surfaces of the via to prevent diffusion of the copper out of the via.
13. The method of claim 12 , wherein the barrier metal layer contacts the substrate.
14. The method of claim 1 , further comprising the steps of:
forming a protection layer on the insulating layer and the second portion of the alloy layer; and
etching an opening the protection layer to expose a predetermined region of the alloy layer.
15. The method of claim 14 , wherein the protection layer comprises silicon nitride or silicon oxynitride.
16. The method of claim 14 , wherein the predetermined region of the alloy layer has a width that is less than a width of the via.
17. The method of claim 14 , wherein removing the reaction layer comprises an anisotropic etching process or a chemical mechanical polishing process.
18. The method of claim 14 , further comprising a cleaning process performed after removing the reaction layer, and a heat treatment process performed at a temperature of 250 to 350° C. for a duration of 10 to 60 minutes after the cleaning process.
19. The method of claim 14 , wherein the alloy layer is completely within the via.
20. The method of claim 19 , wherein a top surface of the alloy layer is lower than a top surface of the insulation layer.