Methods of forming a pattern for a semiconductor device
View Patent ↗Methods of forming a pattern for a semiconductor device are disclosed, wherein a critical dimension (CD) of a pattern can be accurately controlled and, thus, finer critical dimension can be realized. An illustrated example method comprises: forming an etching target layer on a semiconductor substrate; forming a photoresist pattern on the etching target layer; forming polymer spacers on side surfaces of the photoresist pattern to improve side-surface roughness of the photoresist pattern; and etching the etching target layer using the photoresist pattern and the polymer spacers as a mask to form a pattern.
1. A method of forming a pattern for a semiconductor device comprising:
forming a planar etching target layer on a semiconductor substrate;
forming a bottom anti reflective coating (BARC) layer on the planar etching target layer;
forming a photoresist pattern on the BARC layer;
forming polymer spacers on side surfaces of the photoresist pattern and over a top surface of the BARC layer to improve side-surface roughness of the photoresist pattern; and
etching through an entire thickness of the BARC layer and the planar etching target layer using the photoresist pattern and the polymer spacers as a mask to form a semiconductor device pattern with substantially vertical sidewalls.
2. A method as defined in claim 1 , wherein forming the polymer spacers comprises depositing polymers on the side surfaces of the photoresist pattern.
3. A method as defined in claim 2 , wherein depositing comprises exposing the photoresist pattern to a plasma comprising hydrogen bromide gas HBr at a flow rate of about 50 to 100 seem and oxygen gas at a flaw rate of about 5 to 20 seem in a process chamber.
4. A method as defined in claim 2 , wherein a critical dimension of the pattern is controlled by a thickness of the polymer spacers.
5. A method as defined in claim 3 , wherein the process chamber has a pressure of about 3 to 10 mTorr.
6. A method as defined in claim 5 , wherein the process chamber has a source power of about 400 to 800 W and a bias power of about 50 to 100 W.
7. A method as defined in claim 6 , wherein the photoresist pattern comprises an organic material.
8. A method as defined in claim 7 , wherein the plasma reacts with the organic material of the photoresist pattern to form the polymer spacers.
9. A method as defined in claim 1 , comprising etching the BARC layer before etching the planar etching target layer.
10. A method as defined in claim 1 , further comprising forming an insulating layer on the substrate prior to forming the planar etching target layer.
11. A method as defined in claim 10 , wherein the insulating layer comprises an oxide layer.
12. A method as defined in claim 1 , wherein the planar etching target layer comprises a polysilicon layer.
13. A method as defined in claim 1 , wherein forming the photoresist pattern comprises patterning the photoresist layer by photolithography.
14. A method as defined in claim 1 , further comprising removing the photoresist pattern and the polymer spacers by ashing and stripping.
15. A method as defined in claim 10 , wherein etching the planar etching target layer exposes a surface of the insulating layer.
16. A method as defined in claim 1 , wherein the photoresist pattern comprises an organic material.
17. A method as defined in claim 3 , wherein the process chamber is a process chamber of a dry etching equipment.