Granted Patent B2

US 7,329,576 · App. 11/021,639 · Granted Feb 12, 2008

Abstract

Claims (65)

1. A method of forming an isolated lower electrode for a memory array, comprising:

depositing a sacrificial layer within a recess having a base and sidewalls in a structural layer material;

depositing a protective liner over the sacrificial layer;

removing the sacrificial layer and the protective liner from the base of the recess;

depositing a lower electrode within the sacrificial layer and protective layer in the recess;

etching the sacrificial layer within the recess after depositing the lower electrode;

removing the protective liner; and

removing the structural layer material from the memory array after etching the sacrificial layer.

2. The method of claim 1 , wherein depositing the sacrificial layer comprises depositing germanium oxide.

3. The method of claim 1 , wherein depositing the sacrificial layer comprises depositing phosphosilicate glass (PSG).

4. The method of claim 1 , wherein depositing the sacrificial layer comprises depositing a doped oxide.

5. The method of claim 4 , wherein the structural layer comprises substantially undoped oxide.

6. The method of claim 1 , wherein depositing the sacrificial layer comprises depositing a metallic sacrificial layer.

7. The method of claim 6 , wherein depositing the sacrificial layer comprises depositing a metal oxide sacrificial layer.

8. The method of claim 6 , wherein depositing the sacrificial layer comprises depositing a metal nitride sacrificial layer.

9. The method of claim 1 , wherein removing the protective liner and removing the structural layer material are performed simultaneously.

10. The method of claim 1 , wherein etching the sacrificial layer and removing the protective liner are performed simultaneously.

11. A method of forming a capacitor for a DRAM memory cell comprising

forming a recess within a structural layer over an interlayer dielectric layer, wherein the recess has a base and sidewalls;

forming a sacrificial layer along the sidewalls of the recess;

forming a lower electrode within the sacrificial layer in the recess;

doping a portion of the sacrificial layer to form an etch stop;

removing the sacrificial layer above the etch stop after forming the lower electrode;

removing at least a portion of the structural layer after removing the sacrificial layer;

forming a conformal capacitor dielectric over the lower electrode after removing at least a portion of the structural layer; and

forming a conformal upper electrode over the conformal capacitor dielectric.

12. The method of claim 11 , wherein doping a portion of the sacrificial layer comprises:

forming an oxide layer with a high concentration of a dopant within the structural layer;

allowing the dopant to diffuse into a layer of the sacrificial layer.

13. The method of claim 12 , wherein forming the sacrificial layer comprises forming a polysilicon sacrificial layer.

14. The method of claim 12 , wherein the oxide layer comprises a borosilicate glass layer with a dopant concentration by weight of between about 10% and 15%.

15. The method of claim 12 , wherein the oxide layer comprises a borosilicate glass layer with a dopant concentration by weight of between about 11% and 14%.

16. The method of claim 12 , wherein the oxide layer comprises a phosphosilicate glass layer with a dopant concentration by weight of between about 10% and 25%.

17. The method of claim 16 , wherein the oxide layer comprises a phosphosilicate glass layer with a dopant concentration by weight of between about 12% and 20%.

18. The method of claim 11 , wherein doping the portion of the sacrificial layer comprises:

forming a metallic layer with a diffusing metal within the structural layer;

allowing the diffusing metal to diffuse into a layer of the sacrificial layer.

19. The method of claim 18 , wherein forming the sacrificial layer comprises forming a polysilicon sacrificial layer.

20. The method of claim 18 , wherein forming the metallic layer comprises forming a metallic layer with a thickness of between about 50 Å and 1,000 Å.

21. The method of claim 20 , wherein forming the metallic layer comprises forming a metallic layer with a thickness of between about 100 Å and 700 Å.

22. The method of claim 18 , wherein forming the metallic layer comprises forming a tungsten layer.

23. The method of claim 18 , wherein forming the metallic layer comprises forming a titanium oxide layer.

24. The method of claim 18 , wherein forming the metallic layer comprises forming an aluminum oxide layer.

25. The method of claim 11 , wherein doping a portion of the sacrificial layer comprises implanting ions into the sacrificial layer.

26. The method of claim 25 , wherein forming the sacrificial layer comprises forming a polysilicon sacrificial layer.

27. The method of claim 25 , wherein implanting ions comprises implanting argon ions.

28. The method of claim 25 , wherein implanting ions comprises implanting nitrogen ions.

29. The method of claim 25 , wherein implanting ions comprises implanting boron ions.

30. The method of claim 25 , wherein implanting ions comprises implanting phosphorus ions.

31. A method of forming a capacitor in an integrated circuit compnsing

forming a sacrificial layer in a recess in a structural layer, the sacrificial layer having a thickness extending from an outer surface to an inner surface;

forming a lower electrode within the sacrificial layer;

doping a portion of the sacrificial layer, wherein doping creates a doped portion extending through the thickness and an undoped portion extending through the thickness; and

removing one of the doped portion and the undoped portion.

32. The method of claim 31 , further comprising removing the structural layer after removing one of the doped portion and the undoped portion.

33. The method of claim 32 , further comprising forming a conformal dielectric layer and upper electrode over the lower electrode after removing the structural layer.

34. The method of claim 31 , wherein forming the sacrificial layer comprises forming a polysilicon layer.

35. A method of forming a capacitor in an integrated circuit comprising

forming a sacrificial layer in a recess in a structural layer;

forming a lower electrode within the sacrificial layer;

doping a portion of the sacrificial layer, wherein doping creates a doped portion and an undoped portion; and

removing one of the doped portion and the undoped portion, wherein doping the portion of the sacrificial layer comprises forming a dopant collar within the structural layer.

36. The method of claim 35 , wherein forming the dopant collar comprises-forming a metallic collar.

37. The method of claim 35 , wherein forming the dopant collar comprises forming a highly doped oxide collar.

38. The method of claim 31 , wherein forming the sacrificial layer comprises forming an oxide layer.

Assignments (7)