Methods of fabricating semiconductor devices
View Patent ↗Methods of fabricating a semiconductor devices are disclosed. One example method includes forming a gate insulating layer and a gate electrode on a semiconductor substrate; forming first halo implant regions under the gate electrode in the semiconductor substrate by implanting first conduction type impurities; forming low concentration impurity regions for LDD regions under sides of the gate electrode in the semiconductor substrate by implanting second conduction type impurities at a low concentration; forming second halo implant regions under sides of the gate electrode in the semiconductor substrate by implanting first conduction type impurities; forming high concentration impurity regions for source/drain regions in the semiconductor substrate by implanting second conduction type impurities; and forming junction compensation ion regions between the high concentration impurity regions and the second halo implant regions by implanting first conduction type impurities.
1. A method of fabricating a semiconductor device comprising:
forming a gate insulating layer and a gate electrode on a semiconductor substrate;
forming first halo implant regions under the gate electrode in the semiconductor substrate by implanting first conduction type impurities;
forming low concentration impurity regions for LDD regions under sides of the gate electrode in the semiconductor substrate by implanting second conduction type impurities at a low concentration;
forming second halo implant regions under sides of the gate electrode in the semiconductor substrate by implanting first conduction type impurities;
forming high concentration impurity regions for source/drain regions in the semiconductor substrate by implanting second conduction type impurities; and
forming junction compensation ion regions between the high concentration impurity regions and the second halo implant regions by implanting first conduction type impurities.
2. A method as defined by claim 1 , wherein forming first halo implant regions is performed by implanting first conduction type impurities at an angle between about 20° and about 40° with respect to the direction perpendicular to the surface of the semiconductor substrate.
3. A method as defined by claim 2 , wherein forming first halo implant regions is performed by implanting first conduction type impurities with a dose that ranges from about 1.0×10 13 ions/cm 2 to about 5.0×10 14 ions/cm 2 at an implant energy ranging from about 10 keV to about 50 keV.
4. A method as defined by claim 1 , wherein forming first halo implant regions is performed by implanting first conduction type impurities with a dose that ranges from about 1.0×10 13 ions/cm 2 to about 5.0×10 14 ions/cm 2 at an implant energy ranging from about 10 keV to about 50 keV.
5. A method as defined by claim 1 , wherein forming second halo implant regions is performed by implanting first conduction type impurities with a dose that ranges from about 5.0×10 13 ions/cm 2 to about 5.0×10 14 ions/cm 2 at an implant energy ranging from about 5 keV to about 50 keV.
6. A method as defined by claim 1 , wherein forming junction compensation ion regions is performed by implanting first conduction type impurities with a dose that ranges from about 1×10 14 ions/cm 2 to about 1×10 15 ions/cm 2 at an implant energy ranging from about 10 keV to about 60 keV.