MOS transistors and methods of manufacturing the same
View Patent ↗MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.
1. A method of manufacturing a MOS transistor, comprising steps of:
forming a gate insulating layer pattern and a gate on a semiconductor substrate of a first conductivity type where an active region is defined by an isolation layer;
forming an ion implanting buffer layer on the entire surface of the substrate;
forming first source/drain extension regions of a second conductivity type first within the substrate at both sides of the gate by performing a first ion implanting process;
forming second source/drain extension regions of the second conductivity type within the substrate under the first source/drain extension region by performing a second ion implanting process;
forming halo impurity regions of the first conductivity type within the substrate under the edge of the gate by performing a third ion implanting process;
forming a spacer on side walls of the gate; and
forming source/drain regions of the second conductivity type within the substrate at both sides of the spacer by performing a fourth ion implanting process.
2. A method of claim 1 , wherein the second source/drain extension regions have a higher impurity concentration than the first source/drain extension regions.
3. A method of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.
4. A method of claim 3 , wherein the first Ion implanting process is performed at an implanting energy of about 5 to 50 keV and a concentration of about 1×10 14 to 1×10 15 ions/cm 2 using arsenic (As) ions.
5. A method of claim 4 , wherein the second ion implanting process is performed at an implanting energy of about 10 to 50 keV and a concentration of about 5×10 13 to 5×10 14 ions/cm 2 using phosphorus (P) ions.
6. A method of claim 3 , wherein the third ion implanting process is performed in a tilted direction with respect to the substrate.
7. A method as defined in claim 6 , wherein the third ion implanting process is performed at an implanting energy of about 5 to 50 keV and a concentration of about 1×10 14 to 5×10 15 ions/cm 2 using BF 2 ions.
8. A method of claim 7 , wherein the third ion implanting process is performed at a tilt angle of 20 to 30 degrees.
9. A method of claim 1 , wherein the ion implanting buffer layer comprises an oxide layer.
10. A method of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
11. A method of manufacturing a MOS transistor, comprising steps of:
forming a gate insulating layer pattern and a gate on a p-type semiconductor substrate where an active region is defined by an isolation layer;
forming first n-type source/drain extension regions within the substrate at sides of the gate by performing a first ion implanting process;
forming second n-type source/drain extension regions within the substrate under the first source/drain extension regions by performing a second ion implanting process;
forming halo impurity regions of the first conductivity type within the substrate under the edge of the gate by performing a third ion implanting process, wherein the third ion implanting process is performed in a tilted direction with respect to the substrate and at an implanting energy of about 5 to 50 keV and a concentration of about 1×10 14 to 5×10 15 ions/cm 2 using BF 2 ions;
forming a spacer on side walls of the gate; and
forming n-type source/drain regions within the substrate at sides of the spacer by performing a fourth ion implanting process.