IP Library Granted Patent US 7,316,958
Granted Patent B2
US 7,316,958 · App. 11/022,612 · Granted Jan 8, 2008

Masks for fabricating semiconductor devices and methods of forming mask patterns

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Quick Facts
Patent No.
US 7,316,958
App. No.
11/022,612
Granted
Jan 8, 2008
Kind
B2
Abstract

Masks for fabricating a semiconductor device and methods of forming mask patterns are provided which are capable of enhancing the breakdown voltage of the fabricated semiconductor device by accurately correcting a line width pattern error of a semiconductor substrate due to a mask error during a process for forming a well ion implantation mask pattern. A disclosed mask used to manufacture a semiconductor device having complementary N-well and P-well includes: a master mask for the complementary N-well and P-well; and a light-blocking pattern on the master mask, wherein a region of the master mask, which is not a portion of the master mask adjacent to the light-blocking pattern, is etched by a predetermined thickness to have a phase shifting function.

Claims (20)

1. A method of forming a photolithography mask comprising:

forming a light-blocking layer on a light-transmitting mask;

forming a first resist pattern on a portion of the light-blocking layer;

etching an exposed portion of the light-blocking layer to form (i) light-blocking pattern corresponding to one of a complementary N-well and P-well and (ii) a size adjusting region comprising an exposed surface of the light-transmitting mask;

forming a second resist pattern on the light-blocking pattern and a portion of the exposed surface of the light-transmitting mask, including a portion of the size adjusting region; and

partially etching the exposed surface of the light-transmitting mask by a phase shifting depth to form (i) a phase shifted region and (ii) a non-etched region of the size adjusting region, the non-etched region of the size adjusting region being between the light-blocking pattern and the phase shifted region;

wherein the size adjusting region increases a slope of the light intensity at an end portion of the phase shifted region relative to an otherwise identical mask that does not include the size adjusting region.

2. A method as defined in claim 1 , wherein a width of a line exposed by the light-transmitting mask in an exposing process using the second resist pattern is in a range of about 0.2 to about 0.8 μm.

3. A method as defined in claim 1 , wherein widths of lines exposed by the light-transmitting mask in an exposing process using the second resist pattern are not overlapped during respective mask aligning processes for the N-well and P-well.

4. A method as defined in claim 1 , wherein the step of etching the exposed surface of the light-transmitting mask forms a non-etched region of the exposed region of the light-transmitting mask corresponding to the size adjusting region.

5. A method as defined in claim 1 , wherein the non-etched region has a width of about 0.04 μm.

6. A method as defined in claim 1 , further comprising passing light through the light-transmitting mask to form one of the N-well and the P-well.

7. A method as defined in claim 6 , further comprising passing additional light through another light-transmitting mask to form the other of the N-well and the P-well.

8. A method as defined in claim 7 , wherein the step of forming the N-well and P-well forms an overlap region between the N-well and P-well.

9. A method as defined in claim 1 , further comprising forming another light-transmitting mask and forming another light-blocking pattern thereon corresponding to the other of the complementary N-well and P-well.

10. A method as defined in claim 1 , wherein the light-blocking layer has a wide slanted surface.

11. A method as defined in claim 5 , wherein an amplitude of light passing through the non-etched region has a positive component.

12. A method as defined in claim 5 , wherein an amplitude of light passing through the non-etched region has a steep positive component.

13. A method as defined in claim 5 , wherein the intensity of light transmitted through the light-transmitting mask is substantially lower in the non-etched region than a partially etched area of the light-transmitting mask.

14. A method as defined in claim 7 , wherein the overlap region has a constant width.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 21, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017821/0670 →
CHANGE OF NAME Recorded Jun 8, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017749/0335 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2004
From: LEE, JUN SEOK
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 016134/0640 →