Method of fabricating semiconductor device by using sacrifice layer for forming diffusion regions
View Patent ↗The present invention provides a method of fabricating a semiconductor device, by which leakage current is minimized and by which drivability of transistor is sustained. The present invention includes forming a gate pattern having a gate oxide layer underneath on a semiconductor substrate, forming a first oxide layer on the substrate including the gate pattern, forming lightly doped regions in the semiconductor substrate to be aligned with the gate pattern, forming a second oxide layer on the first oxide layer, forming a spacer on the second oxide layer over a sidewall of the gate pattern, forming a sacrifice layer over the substrate including the spacer, forming source and drain regions in the substrate to be aligned with the gate pattern and to be partially overlapped with the lightly doped regions, respectively, and removing the sacrifice insulating layer and portions of the first and second oxide layers failing to be covered with the spacer.
1. A method of fabricating a semiconductor device, comprising the steps of:
forming a gate pattern having a gate oxide layer underneath on a semiconductor substrate;
forming a first oxide layer on the substrate including the gate pattern;
forming lightly doped regions in the semiconductor substrate to be aligned with the gate pattern;
forming a second oxide layer on the first oxide layer;
forming a spacer on the second oxide layer over a sidewall of the gate pattern;
forming a sacrifice layer over the substrate including the spacer;
forming source and drain regions in the substrate by ion implantation using the gate pattern, the first oxide layer, the second oxide layer, and the spacer, and the sacrifice layer as an ion implantation mask, the source and drain regions to be aligned with the gate pattern and to be partially overlapped with the lightly doped regions, respectively; and
removing the sacrifice layer and portions of the first and second oxide layers not covered with the spacer.
2. The method of claim 1 , further comprising the step of forming a silicide layer on the source and drain regions and a topside of the gate pattern.
3. The method of claim 1 , wherein the sacrifice layer is formed of a material having high etch selectivity from the spacer.
4. The method of claim 3 , wherein the sacrifice layer is formed of TEOS.
5. The method of claim 1 , wherein the lightly doped regions are formed by ion implantation using the gate pattern as an ion implantation mask.