Semiconductor memory device for testifying over-driving quantity depending on position
A semiconductor memory device is capable of testifying over-driving quantity depending on position. A semiconductor memory device includes a plurality of in-bank over-drivers for temporarily applying a high voltage to a normal power that is supplied to a memory array cell within a bank; a plurality of out-bank over-drivers arranged outside the bank for temporarily applying the high voltage to the normal power that is supplied to the bank; a plurality of PERI over-drivers arranged at the peripheral area for temporarily applying the high voltage to the normal power; a mode register set for receiving a signal to select one of the over-drivers; and a decoder activated in response to a test mode signal for decoding the set value of the MRS to selectively drive the over-driver arranged at a desired position and having desired driving power among the in-bank and out-bank over-drivers and the PERI over-drivers.
1. A semiconductor memory device for effectively testing a driving power, comprising:
a plurality of bank over-driving circuits, each for overdriving each corresponding bank;
a plurality of peri over-driving circuits, each having different over-driving power and different positions; and
a decoder for decoding a preset value of an MRS (Mode Register Set) in order to output a plurality of control signals, each for controlling a corresponding one among the plurality of bank over-driving circuits and the plurality of peri over-driving circuits in a test mode.
2. The semiconductor memory device as recited in claim 1 , wherein, in the test mode, a predetermined over-driving circuit with a desired position and a driving power the plurality of bank over-driving circuits and the plurality of peri over-driving circuits is selectively driven through preset of the MRS (Mode Register Set) so as to determine a driving power that is required for a predetermined part in the semiconductor memory device.
3. The semiconductor as recited in claim 2 , wherein the MRS is an extended mode register set (EMRS).
4. A semiconductor memory device, comprising:
a plurality of in-bank over-drivers for temporarily applying a high voltage to a normal power that is supplied to a memory array cell within a bank;
a plurality of out-bank over-drivers arranged outside the bank for temporarily applying the high voltage to the normal power that is supplied to the bank;
a plurality of PERI over-drivers arranged at a peripheral area for temporarily applying the high voltage to the normal power;
a mode register set for receiving a signal to select one of the over-drivers; and
a decoding means activated in response to a test mode signal for decoding the set value of the MRS to selectively drive the over-driver arranged at a desired position and having a desired driving power among the in-bank and out-bank over-drivers and the PERI over-drivers.
5. The semiconductor as recited in claim 4 , wherein the MRS is an EMRS.