MOS transistor and method of manufacturing the same
View Patent ↗A metal oxide semiconductor (MOS) transistor and a method of manufacturing the same are disclosed. An example MOS transistor includes a semiconductor substrate of a first conductivity type where an active region is defined, a gate insulating layer pattern and a gate formed on the active region of the substrate, a spacer formed on side walls of the gate, and source/drain extension regions of a second conductivity type formed within the substrate at both sides of the gate. The example MOS transistor further includes source/drain regions of the second conductivity type formed within the substrate at both side of the spacer and punch-through suppression regions of the first conductivity type formed within the active of the substrate. The punch-through suppression regions surround the source/drain extension regions and the source/drain regions under the gate.
1. A method of manufacturing a MOS transistor, comprising:
subsequently forming a gate insulating layer and a gate conductive layer on a semiconductor substrate having a first conductivity type where an active region is defined by an isolation layer;
implanting first impurities of the first conductivity type within the active region of the substrate by performing a first ion implanting process;
forming a gate and a gate insulating layer pattern on the active region of the substrate by patterning the gate insulating layer and the gate conductive layer;
implanting second impurities of a second conductivity type within the substrate at both sides of the gate by performing a second ion implanting process;
implanting third impurities of the first conductivity type within the substrate under the edge of the gate by performing a third ion implanting process;
forming a spacer on side walls at the gate;
forming a first punch-through suppression region containing the first impurities, source/drain extension regions containing the second impurities, and a second punch-through suppression region containing the third impurities by performing a first thermal treatment process;
implanting fourth impurities of the second conductivity type within the substrate at both sides at the spacer by performing a fourth ion implanting process; and
forming source/drain regions containing the fourth impurities by performing a second thermal treatment process.
2. The method of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
3. The method of claim 2 , wherein the first ion implanting process is performed at an implanting energy of about 10 to 70 keV and a concentration of 1×10 13 to 1×10 14 ions/cm 2 using phosphorus (P) ions as the first impurities.
4. The method of claim 2 , wherein the third ion implanting process is performed to a tilted direction with respect to the substrate.
5. The method of claim 4 , wherein the third ion implanting process is performed at an implanting energy of about 20 to 80 keV and a concentration of 1×10 14 to 5×10 14 ions/cm 2 using arsenic (As) ions as the third impurities.
6. The method of claim 5 , wherein the third ion implanting process is performed at a tilt angle of 20 to 30 degrees.
7. The method of claim 1 , wherein the first thermal treatment process is performed at a temperature of about 800 to 1000° C. in an N 2 ambient for 10 to 30 seconds by an RTP.
8. The method of claim 1 , wherein the second thermal treatment process is performed at a temperature of about 900 to 1050° C. in an N 2 ambient for 10 to 30 seconds by an RTP.
9. The method of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.