IP Library Granted Patent US 7,448,013
Granted Patent B2
US 7,448,013 · App. 11/023,357 · Granted Nov 4, 2008

Method and apparatus for facilitating circuit design

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Quick Facts
Patent No.
US 7,448,013
App. No.
11/023,357
Granted
Nov 4, 2008
Kind
B2
Abstract

There is disclosed a system for designing circuits which involves pre-placing delay elements between circuit components susceptible to shoot-through due to effects of clock skew, each delay element having a physical form and at least one input terminal and at least one output terminal; determining which delay elements are not critical in preventing shoot-through; removing non-critical delay elements from the circuit; and replacing each removed delay element with a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and output of the delay element. This wire cell has the effect of removing the delay element from the circuit without having to reposition the circuit components. This has the result that it is not necessary to re-position circuit components on the removal of delay elements and then to re-evaluate the circuit performance. Circuit design can be significantly improved.

Claims (40)

1. A method for designing a circuit, comprising the steps of:

pre-placing delay elements between circuit components, each delay element comprising at least one input terminal and at least one output terminal;

analyzing the circuit to identify non-critical delay elements that are not needed for circuit operation;

removing a non-critical delay element from the circuit; and

replacing the removed delay element with a conductor located between positions of an input terminal and an output terminal of the removed delay element without changing said positions.

2. The method of claim 1 , wherein the removed delay element is replaced by a wire.

3. The method of claim 1 , wherein the removed delay element is replaced by a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and an output of the delay element.

4. The method of claim 1 , wherein the pre-placing, analyzing, removing and replacing steps are initially carried out in simulation.

5. Computer apparatus for designing a circuit, including:

means for pre-placing delay elements between components in a circuit layout, each delay element comprising at least one input terminal and at least one output terminal;

means for identifying non-critical delay elements that are not needed for circuit operation;

means for removing a non-critical delay element from the circuit; and

means for replacing the removed delay element with a conductor located between positions of an input terminal and an output terminal of the removed delay element without changing said positions.

6. Apparatus according to claim 5 , wherein said means for replacing replaces the removed delay element with a wire.

7. Apparatus according to claim 5 , wherein said means for replacing replaces the removed delay element by a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and an output of the delay element.

8. Apparatus according to claim 5 , wherein said means for pre-placing, said means for identifying, said means for removing, and said means for replacing are in hardware form.

9. Apparatus according to claim 5 , wherein said means for pre-placing, said means for identifying, said means for removing, and said means for replacing are in software form.

10. A computer program product comprising a computer usable medium having executable code to execute a process for designing a circuit, the process comprising:

pre-placing delay elements between circuit components, each delay element comprising at least one input terminal and at least one output terminal;

identifying non-critical delay elements that are not needed for circuit operation;

removing a non-critical delay element from the circuit; and

replacing the removed delay element with a conductor located between positions of an input terminal and an output terminal of the removed delay element without changing said positions.

11. A computer program product according to claim 10 , wherein the removed delay element is replaced by a wire.

12. A computer program product according to claim 10 , wherein the removed delay element is replaced by a cell having a physical form equivalent to a physical form of the removed delay element and a wire connection between an input and an output of the cell equivalent to an input and an output of the delay element.

13. A computer program product according to claim 10 , wherein the program is stored in a physical memory or other computer readable medium.

14. A method of designing a circuit, including the steps of:

pre-placing delay elements between circuit components, each delay element comprising at least one input terminal and at least one output terminal;

identifying non-critical delay elements that are not needed for circuit operation;

removing a non-critical delay element from the circuit; and

replacing the removed delay element with a cell having a physical form equivalent to a physical form of the removed delay element and a wire connection between an input and an output of the cell in the same position as an input and an output of the removed delay element.

15. Apparatus for designing a circuit, including;

means for pre-placing delay elements between circuit components, each delay element representing a physical form and comprising at least one input terminal and at least one output terminal;

means for identifying non-critical delay elements that are not needed for circuit operation;

means for removing non-critical delay element from the circuit; and

means for replacing the removed delay element with a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell in the same position as an input and an output of the delay element.

16. A computer program product comprising a computer usable medium having executable code to execute a process for designing a circuit, the process comprising:

pre-placing delay elements between circuit components, each delay element representing a physical form and comprising at least one input terminal and at least one output terminal;

identifying non-critical delay elements that are not needed for circuit operation;

removing a non-critical delay element from the circuit; and

replacing the removed delay element with a cell having a physical form equivalent to the physical form of the removed delay element and a wire connection between an input and an output of the cell in the same position as an input and an output of the delay element.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2004
From: WALLACE, ANDREW P.
To: BROADCOM CORPORATION
Reel/Frame 016136/0827 →