Data output controller for memory device
Disclosed is a data output controller for a memory device. The data output controller for a memory device, the data output controller comprising a control part for generating a first pulse control signal and a second pulse control signal through a combination of an internal clock signal outputted from a DLL means and a pulse signal enabled during a time in which a number of clocks of the internal clock signal, corresponding to a burst length of the memory device, is counted, a data output buffer unit controlled by the first plus control signal, and a data strobe signal buffer unit controlled by the second pulse control signal.
1. A data output controller for a memory device, comprising:
a first switching part turned on/off by an internal clock signal outputted from a DLL means and receiving a first pulse signal enabled during a predetermined time in synchronization with the internal clock signal;
a latch part for latching the first pulse signal passing through the first switching part;
a second switching part turned on/off by the internal clock signal and receiving a latch part output signal outputted from the latch part;
a first decoding part for receiving the latch part output signal and a second switching part output signal outputted from the second switching part and performing an ‘AND’ operation of the received latch part output signal and the received second switching part output signal;
a second decoding part for receiving a first decoding part output signal and the internal clock signal and performing an ‘AND’ operation of the received first decoding part output signal and the internal clock signal;
a third decoding part for receiving the latch part output signal and the internal clock signal and performing an ‘AND’ operation of the received latch part output signal and the internal clock signal;
a data output buffer unit controlled by the second decoding part output signal; and
a data strobe signal buffer unit controlled by a third decoding part output signal.
2. The data output controller as claimed in claim 1 , wherein the first pulse signal is enabled during a time in which the number of clocks of the internal clock signal, corresponding to a burst length of the memory device, is counted.
3. The data output controller as claimed in claim 1 , wherein windows of data sequentially outputted from the data output buffer unit have the same width.
4. The data output controller as claimed in claim 1 , wherein the first pulse signal is enabled during a time in which the number of clocks of the internal clock signal, corresponding to a burst length of the memory device, is counted, and the latch part output signal is obtained by delaying the first pulse signal by a predetermined time and is enabled during a toggling duration of the internal clock signal corresponding to CAS latency of the memory device.
5. The data output controller as claimed in claim 4 , wherein a first rising edge occurring time point of the second decoding part output signal is later than a first rising edge occurring time point of the third decoding part output signal.
6. The data output controller as claimed in claim 5 , wherein a data strobe signal is outputted from the data strobe signal buffer unit in synchronization with a rising edge and a falling edge of the third decoding part output signal.
7. The data output controller as claimed in claim 5 , wherein data are outputted from the data output buffer unit in synchronization with a rising edge and a falling edge of the second decoding part output signal.
8. A data output controller for a memory device, the data output controller comprising:
a control part for generating a first pulse control signal and a second pulse control signal through a combination of an internal clock signal outputted from a DLL means and a pulse signal enabled during a time in which a number of clocks of the internal clock signal, corresponding to a burst length of the memory device, is counted;
a data output buffer unit controlled by the first pulse control signal; and
a data strobe signal buffer unit controlled by the second pulse control signal wherein the first pulse control signal and the second pulse control signal are not the same.
9. The data output controller as claimed in claim 8 , wherein the first pulse control signal and the second pulse control signal are valid during the burst length, a first pulse rising edge occurring time point of the first pulse control signal is faster than a first pulse rising edge occurring time point of the second pulse control signal, and falling edges and rising edges of the first pulse control signal coincide with those of the second pulse control signal except for rising edges of first pulses of the first pulse control signal and the second pulse control signal.