Semiconductor memory apparatus
View Patent ↗A semiconductor memory apparatus including a simple circuit configuration and is capable of randomly accessing fuse data. A fuse cell 30 including a fuse 31 is connected to a pair of bit lines of a memory circuit. The fuse 31 and a fuse data output circuit (which includes a resistor 32 and an inverter 33 ) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch 34 . By allowing a column decoder 12 for selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.
1. A semiconductor memory apparatus, comprising:
a plurality of memory cells;
bit lines which connect the memory cells;
a sense amplifier for amplifying a signal on a corresponding bit line;
a selection circuit for selecting at least one bit line from the bit lines;
a data line to be connected to the bit line selected by the selection circuit;
a plurality of fuses;
fuse data output circuits each for outputting a signal in accordance with a disconnection/non-disconnection state of a corresponding fuse;
a fuse selection circuit for selecting at least one circuit from the fuse data output circuits; and
a fuse selection switch for connecting, when reading corresponding fuse data, a corresponding fuse data output circuit selected by the fuse selection circuit to the data line.
2. A semiconductor memory apparatus, comprising:
a plurality of memory cells;
bit lines to be connected to the memory cells;
a sense amplifier for amplifying a signal on a corresponding bit line;
a selection circuit for selecting at least one bit line from the bit lines;
a data line to be connected to the bit line selected by the selection circuit;
a plurality of fuses;
fuse data output circuits each for outputting a signal in accordance with a disconnection/non-disconnection state of a corresponding fuse; and
a fuse selection switch for connecting, when reading corresponding fuse data, a corresponding fuse data output circuit to a corresponding bit line selected by the selection circuit.
3. The semiconductor memory apparatus according to claim 2 , wherein
the number of fuses is less than the number of bit lines, and
the bit lines include:
a first bit line to be connected to a corresponding fuse data output circuit through a corresponding fuse selection switch; and
a second bit line which is not connected to either a corresponding fuse selection switch or a corresponding fuse data output circuit.
4. The semiconductor memory apparatus according to claim 3 , wherein the bit lines include a plurality of the first bit lines and a plurality of the second bit lines.
5. The semiconductor memory apparatus according to claim 3 , wherein
the bit lines include a plurality of the first bit lines and a plurality of the second bit lines, and
the first bit lines and the second bit lines are all arranged in a region where the memory cells are arranged.
6. The semiconductor memory apparatus according to claim 3 , wherein
the bit lines include a plurality of the first bit lines and a plurality of the second bit lines, and
each second bit line is fixed, when reading corresponding fuse data, to a predetermined potential corresponding to a low level or a high level.
7. The semiconductor memory apparatus according to claim 3 , wherein the sense amplifier amplifies a signal on a corresponding first bit line and does not amplify a signal on a second bit line, when reading corresponding fuse data.
8. The semiconductor memory apparatus according to claim 2 , further comprising:
an output control circuit for controlling an output of the data line, wherein
the memory cells include:
a data storage memory cell for storing normal data; and
an error correction memory cell for storing error correction data, wherein
the output control circuit outputs, when reading memory data, a result obtained by performing error correction on data read from a corresponding data storage memory cell and a corresponding error correction memory cell, and outputs, when reading fuse data, data read from a corresponding data storage memory cell as it is.
9. The semiconductor memory apparatus according to claim 2 , wherein the sense amplifier amplifies, when reading corresponding memory data, a signal on a corresponding bit line, and does not amplify, when reading corresponding fuse data, a signal on a corresponding bit line.