Semiconductor device and method of manufacturing the same
View Patent ↗Provided is a semiconductor device capable of reducing the resistance of the gate electrode of a transistor. The semiconductor device comprises a semiconductor substrate, a gate oxide film formed on the substrate, a gate formed on the gate oxide film, and a metal silicide layer formed on the top surface and the upper side surface of the gate.
1. A method of manufacturing a semiconductor device, comprising steps of:
forming a gate structure in which a gate oxide film, a gate, a first buffer layer and a hard mask layer are sequentially deposited on a semiconductor substrate;
forming a second buffer layer of a same material as the first buffer layer on the entire surface of the semiconductor substrate so as to cover a top surface and side surfaces of the gate structure;
forming a spacer above the second buffer layer on sides of the gate structure without removing a part of the second buffer layer;
forming an insulating layer on the entire surface of the semiconductor substrate including the second buffer layer;
planarizing the insulating layer sufficiently to remove a first portion of the second buffer layer and expose the hard mask layer;
removing the exposed hard mask layer and a portion of the spacer;
selectively removing a portion of the first buffer layer exposed by the removal of the hard mask layer and a second portion of the second buffer layer to expose the top surface and the upper side surface of the gate and form an opening between the gate and the spacer; and
forming a metal silicide layer on the exposed top and upper side surfaces of the gate in the opening.
2. The method of claim 1 , wherein the first buffer layer and the second buffer layer each comprise a silicon oxide.
3. The method of claim 2 , wherein the hard mask layer and the spacer each comprise silicon nitride.
4. The method of claim 1 , wherein the planarizing step is performed so that the insulating layer has a height that is lower than that of the hard mask layer.
5. The method of claim 4 , wherein the planarizing comprises (i) chemical mechanical polishing using a time polishing or the hard mask as an etching end point, or (ii) etching back using the hard mask layer as the etching end point.
6. The method of claim 1 , wherein the metal silicide layer comprises a silicide of any one of titanium (Ti), titanium nitride (TiN), cobalt (Co), nickel (Ni), platinum (Pt), and tungsten (W).
7. The method of claim 1 , wherein the gate has a thickness of from about 260 Å to 1800 Å.
8. The method of claim 7 , wherein the first buffer layer has a thickness of from about 150 Å to 300 Å.
9. The method of claim 8 , wherein the hard mask layer has a thickness of from about 1000 Å to 1500 Å.
10. The method of claim 7 , wherein the hard mask layer has a thickness of from about 1000 Å to 1500 Å.
11. The method of claim 1 , further comprising ion implanting source and drain regions after formation of the spacer on the second buffer layer.
12. The method of claim 1 , wherein the insulating layer comprises a silicon oxide.
13. The method of claim 1 , wherein removing the hard mask layer comprises dry etching with a fluorine based gas and an additive gas comprising oxygen, nitrogen, and/or helium.
14. The method of claim 13 , wherein removing the first buffer layer comprises a wet etching process using dilute hydrofluoric acid.
15. The method of claim 13 , wherein removing the first buffer layer comprises dry etching with a fluorine based gas and an additive gas comprising oxygen, nitrogen, and/or helium.
16. The method of claim 1 , wherein removing the first buffer layer comprises a wet etching process using dilute hydrofluoric acid.
17. The method of claim 1 , wherein removing the first buffer layer comprises dry etching with a fluorine based gas and an additive gas comprising oxygen, nitrogen, and/or helium.
18. The method of claim 3 , wherein the etch selectivity of silicon nitride to silicon oxide is from about 3:1 to 100:1.
19. The method of claim 1 , wherein forming said metal silicide comprises depositing a metal on said gate, remaining portions of said first buffer layer and said second buffer layer, and said insulating layer, and heating or annealing to form said metal silicide.
20. The method of claim 19 , wherein said metal silicide is formed only on the exposed top and upper surfaces of said gate.