IP Library Granted Patent US 7,312,641
Granted Patent B2
US 7,312,641 · App. 11/024,257 · Granted Dec 25, 2007

Sense amplifiers with high voltage swing

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Quick Facts
Patent No.
US 7,312,641
App. No.
11/024,257
Granted
Dec 25, 2007
Kind
B2
Abstract

A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

Claims (50)

1. A sense amplifier comprising:

a reference voltage generator for generating a reference output voltage;

a core output voltage generator for generating a core output voltage, the core output voltage generator including:

a core front-end stage coupled to a current conducting device for converting a current through the current conducting device to a core bit voltage; and

a core back-end stage coupled to the core front-end stage for converting the core bit voltage to the core output voltage having higher voltage swing from the core bit voltage;

a comparator for generating an output signal from comparing the reference output voltage with the core output voltage;

a plurality of core output voltage generators; and

a plurality of comparators with each comparator being coupled to the reference output voltage generator for generating a respective output signal from comparing the reference output voltage to a respective core output voltage generated by a respective one of the core output voltage generators.

2. A sense amplifier comprising:

a reference voltage generator for generating a reference output voltage;

a core output voltage generator for generating a core output voltage, the core output voltage generator including:

a core front-end stage coupled to a current conducting device for converting a current through the current conducting device to a core bit voltage; and

a core back-end stage coupled to the core front-end stage for converting the core bit voltage to the core output voltage having higher voltage swing from the core bit voltage;

an amplifier regulation transistor having a drain coupled to the current conducting device at a node having the core bit voltage generated thereon and having a source coupled to a power supply; and

a core feed-back regulator coupled to a gate and the drain of the amplifier regulation transistor for maintaining the core bit voltage.

3. The sense amplifier of claim 2 , wherein the core back-end stage includes:

a first amplifier transistor having a gate coupled to the gate of the amplifier regulation transistor, and having a source coupled to the power supply; and

a second amplifier transistor having a drain coupled to the drain of the first amplifier transistor, and having a gate and the drain coupled together at an output node with the core output voltage generated thereon.

4. The sense amplifier of claim 2 , wherein the core back-end stage includes:

a first amplifier transistor having a gate coupled to the gate of the amplifier regulation transistor, and having a source coupled to the power supply; and

an amplifier bias resistor coupled between a drain of the first amplifier transistor and a ground node.

5. The sense amplifier of claim 2 , wherein the core back-end stage includes:

a first amplifier transistor having a gate coupled to the gate of the amplifier regulation transistor, and having a source coupled to the power supply; and

a second amplifier transistor having a gate with the reference output voltage applied thereon, and having a source coupled to a ground node, and having a drain coupled to a drain of the first amplifier transistor at an output node with the core output voltage generated thereon.

6. The sense amplifier of claim 2 , wherein the core back-end stage includes:

a first amplifier transistor having a gate coupled to the gate of the amplifier regulation transistor, and having a source coupled to the power supply; and

a second amplifier transistor having a gate with the reference output voltage applied thereon, and having a source coupled to a ground node via an amplifier noise immunity resistor, and having a drain coupled to a drain of the first amplifier transistor at an output node with the core output voltage generated thereon.

7. The sense amplifier of claim 2 , wherein the reference voltage generator includes:

a reference front-end stage coupled to a reference cell for converting a reference current through the reference cell to a reference bit voltage; and

a reference back-end stage coupled to the reference front-end stage for converting the reference bit voltage to the reference output voltage.

8. The sense amplifier of claim 7 , wherein the reference front-end stage includes:

a reference regulation transistor having a drain coupled to the reference cell at a node having the reference bit voltage generated thereon and having a source coupled to the power supply.

9. The sense amplifier of claim 7 , wherein the reference front-end stage further includes:

a reference feed-back regulator coupled to a gate and the drain of the reference regulation transistor for maintaining the reference bit voltage.

10. The sense amplifier of claim 7 , wherein the reference back-end stage includes:

a first reference transistor having a gate coupled to the gate of the reference regulation transistor and having a source coupled to the power supply; and

a second reference transistor having a drain coupled to a drain of the first reference transistor, and having a gate and the drain coupled together at an output node with the reference output voltage generated thereon.

11. The sense amplifier of claim 8 , wherein the reference back-end stage includes:

a first reference transistor having a gate coupled to the gate of the reference regulation transistor and having a source coupled to the power supply; and

a second reference transistor having a drain coupled to a drain of the first reference transistor, having a gate and the drain coupled together at an output node with the reference output voltage generated thereon, and having a source coupled to a ground node.

12. The sense amplifier of claim 8 , wherein the reference back-end stage includes:

a first reference transistor having a gate coupled to the gate of the reference regulation transistor and having a source coupled to the power supply; and

a reference bias resistor coupled between a drain of the first reference transistor and a ground node.

13. The sense amplifier of claim 8 , wherein the reference back-end stage includes:

a first reference transistor having a gate coupled to the gate of the reference regulation transistor and having a source coupled to the power supply; and

a second reference transistor having a drain coupled to a drain of the first reference transistor, having a gate and the drain coupled together at an output node with the reference output voltage generated thereon, and having a source coupled to a ground node via a reference noise immunity resistor.

14. The sense amplifier of claim 2 , further comprising:

a comparator for generating an output signal from comparing the reference output voltage with the core output voltage.

15. The sense amplifier of claim 2 , wherein the current conducting device is a core cell of a memory device.

16. The sense amplifier of claim 2 , wherein the core front-end stage includes the amplifier regulation transistor.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES LLC
Reel/Frame 059721/0467 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036037/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2004
From: AKAOGI, TAKAO; WADHWA, SAMEER; ACHTER, MICHAEL; VENKATESH, BHIMACHAR
To: SPANSION LLC
Reel/Frame 016138/0945 →