Method for forming metal pattern to reduce contact resistivity with interconnection contact

1. A method for forming a metal pattern in a semiconductor device, comprising the steps of:

forming an interconnection contact passing through a lower insulating layer on a semiconductor substrate;

forming an upper insulating layer covering the interconnection contact;

forming a first photoresist pattern on the upper insulating layer;

forming a groove having a same line width as a damascene trench by etching a portion of the upper insulating layer using the first photoresist pattern as an etch mask, the groove comprising two sidewalls and a depth less than a thickness of the upper insulating layer;

forming a spacer layer with a liner shape according to a profile of the groove, the spacer layer being formed out of a same material as the upper insulating layer;

forming a pair of spacers on both sidewalls of the groove by performing an anisotropic dry etching process on the spacer layer;

forming a second photoresist pattern on the upper insulating layer, the second photoresist pattern having the same line as the first photoresist pattern;

forming the damascene trench by etching the pair of spacers, the upper insulating layer and a portion of the lower insulating layer using the second photoresist pattern as an etch mask, wherein the damascene trench comprises a substantially inclined bottom surface for exposing a top surface and portions of both sidewalls of the interconnection contact; and

forming a metal pattern with which the damascene trench is filled, wherein the metal pattern is electrically connected to the interconnection contact.

2. The method of claim 1 , wherein the upper insulating layer and spacer layer are formed of a silicon oxide or a silicon nitride material.

3. The method of claim 1 , wherein the step of forming an interconnection contact includes forming the interconnection contact with a tungsten layer.

4. The method of claim 3 , wherein the step of forming the metal pattern includes: forming a copper layer filling the damascene trench; and smoothing the copper layer.

5. The method of claim 4 , wherein the step of forming a copper layer includes: forming a barrier metal layer within the damascene trench, the barrier metal layer including a Ta/TaN layer covering an exposed portion of the interconnection contact; and forming the copper layer on the barrier metal layer, the copper layer including a seed layer.

6. A method for forming a metal pattern in a semiconductor device, comprising:

forming an interconnection contact passing through a lower insulating layer on a semiconductor substrate;

forming an upper insulating layer covering the interconnection contact;

forming a first photoresist pattern on the upper insulating layer;

forming a groove having a same line width as a damascene trench by etching a portion of the upper insulating layer using the first photoresist pattern as an etch mask, the groove comprising two sidewalls and a depth less than a thickness of the upper insulating layer;

forming a spacer layer with a liner shape according to a profile of the groove, the spacer layer being formed out of a same material as the upper insulating layer;

forming a pair of spacers on both sidewalls of the groove by performing an anisotropic dry etching process on the spacer layer;

forming a second photoresist pattern on the upper insulating layer, the second photoresist pattern having the same line as the first photoresist pattern;

forming the damascene trench by etching the pair of spacers, the upper insulating layer and a portion of the lower insulating layer using the second photoresist pattern as an etch mask, wherein the damascene trench comprises a substantially inclined bottom surface for exposing a top surface and portions of both sidewalls of the interconnection contact; and

forming a metal pattern with which the damascene trench is filled, wherein the metal pattern is electrically connected to the interconnection contact and includes a substantially inclined bottom surface.