Semiconductor device having a dual-damascene gate and manufacturing method thereof

1. A method of manufacturing a semiconductor device having a dual-damascene gate, comprising steps of:

forming lightly doped drain (LDD) regions by forming a gate oxide film on a semiconductor substrate and implanting low-concentration impurities in the semiconductor substrate in accordance with a predetermined LDD pattern;

forming a nitride film on the gate oxide film and forming a wide nitride film in accordance with a wide nitride pattern;

forming a narrow nitride film by a narrow etching process on the wide nitride film in accordance with a predetermined narrow nitride film pattern;

forming a dual-damascene gate by depositing a polysilicon layer on an exposed entire surface and smoothing the deposited polysilicon layer until a top surface of the nitride film is exposed;

forming a gate electrode by removing a predetermined portion of the polysilicon layer;

forming a sidewall nitride film on the gate electrode by etching the exposed nitride film in accordance with a nitride film pattern; and

forming source/drain regions by performing an ion implantation process on source/drain active regions.

2. The method of claim 1 , wherein the step of forming a wide nitride film includes forming the wide nitride film with a thickness of about 2,500 Å to about 3,000 Å and etching the nitride film exposed by the etching pattern until a thickness of the nitride film of about 500 Å to about 1,000 Å remains.

3. The method of claim 1 , wherein the step of forming a dual-damascene gate includes depositing the polysilicon layer using a chemical vapor deposition (CVD) method.

4. The method of claim 1 , further comprising a step of controlling a critical dimension (CD) of the gate by the narrow nitride film formed by the narrow etching process.

5. The method of claim 1 , wherein the step of forming a dual-damascene gate includes forming the dual-damascene gate by depositing the polysilicon layer with a CVD method and removing a depth of the polysilicon layer of about 500 Å to about 1,000 Å with a chemical mechanical polishing (CMP) method.

6. The method of claim 1 , wherein the step of forming a gate electrode includes forming the gate electrode by performing a blanket etching process using an etching selectivity between the gate electrode and the sidewall nitride film to remove a depth of an upper portion of the polysilicon layer of about 300 Å to about 500 Å.

7. The method of claim 1 , further comprising a step of forming a silicide on the gate electrode and source/drain regions.

8. The method of claim 7 , wherein the step of forming a silicide comprises steps of:

forming a metallic film by depositing metal ions on an entire surface of the semiconductor substrate including the gate electrode;

forming a metallic silicide film on the gate electrode and the source/drain regions by reacting silicon ions of the semiconductor substrate with the metal ions of metallic film; and

selectively removing a portion of the metallic film where the metal ions do not react with the silicon ions.

9. The method of claim 8 , wherein the step of forming a metallic film includes forming a metallic film with a thickness of about 200 Å to about 400 Å by a sputtering method.

10. The method of claim 8 , wherein the step of selectively removing a portion of the metallic film includes using a wet etchant including a mixed solution of a hydrogen peroxide (H 2 O 2 ) solution and a sulfuric acid (H 2 SO 4 ) solution.