IP Library Granted Patent US 7,435,669
Granted Patent B2
US 7,435,669 · App. 11/024,678 · Granted Oct 14, 2008

Method of fabricating transistor in semiconductor device

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Quick Facts
Patent No.
US 7,435,669
App. No.
11/024,678
Granted
Oct 14, 2008
Kind
B2
Abstract

A method of fabricating a transistor in a semiconductor device. A gate oxide layer and a gate are formed on a semiconductor substrate. An oxide layer and a silicon nitride layer are stacked on the substrate. The stacked oxide and silicon nitride layers are etched back to expose a surface of the substrate. The silicon nitride layer is removed to form a gate sidewall spacer. Impurity ions are implanted into the substrate through the exposed surface of the substrate.

Claims (14)

1. A method of fabricating a transistor in a semiconductor device, comprising:

forming a gate oxide layer and a gate on a semiconductor substrate;

stacking an oxide layer and a silicon nitride layer on the substrate;

etching back the stacked oxide and silicon nitride layers to expose a surface of the substrate;

removing the silicon nitride layer to form a gate sidewall spacer;

oxidizing the exposed surface of the substrate only to adjust an amount of impurity ions to be implanted;

implanting impurity ions into the substrate through the exposed surface of the substrate;

performing silicidation on the substrate by using the gate sidewall spacer as a silicidation barrier;

forming a premetal dielectric layer over the substrate; and

performing wiring on the substrate.

2. The method according to claim 1 , wherein during the step of implanting impurity ions a density and depth profile of the implanted impurity ions are controlled using a thickness of the oxide layer.

3. The method according to claim 1 , wherein during the step of removing the silicon nitride layer a size of the gate sidewall spacer is controlled using a thickness of the silicon nitride layer.

4. The method according to claim 1 , wherein during the step of implanting impurity ions a range of the implanted impurity ions is controlled using a size of the gate sidewall spacer.

5. The method according to claim 1 , wherein during the step of removing the silicon nitride layer the gate sidewall spacer is formed to prevent the impurity ions from diffusing beneath the gate oxide layer.

Assignments (2)
CHANGE OF NAME Recorded May 23, 2006
From: DONGBU-ANAM SEMICONDUCTOR, INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017663/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2004
From: KIM, DAE KYEUN
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 016139/0364 →