Method of fabricating split gate flash memory device

1. A method of fabricating a split gate flash memory device, comprising the steps of:

forming a pair of first gate patterns on a semiconductor substrate in an active area a prescribed distance from each other;

forming an etch-resistant layer pattern covering confronting sidewalls of the pair of first gate patterns and covering a surface of the substrate corresponding to the prescribed distance;

forming an insulating layer on exposed surfaces of the pair of first gates;

forming a pair of second gate patterns over the pair of first gate patterns, respectively, not overlapping the etch-resistant layer;

removing the etch-resistant layer; and

forming doped regions in the substrate aligned with the pair of first and second gate patterns, respectively.

2. The method of claim 1 , wherein the step of forming a pair of first gate patterns includes a step of forming a cap layer covering each of the pair of first gate patterns.

3. The method of claim 2 , wherein the step of forming a cap layer includes forming the cap layer of an oxide layer and a nitride layer.

4. The method of claim 1 , wherein the step of forming a pair of second gate patterns includes anisotropic etching a conductor layer deposited over the substrate including the etch-resistant layer and the first gate patterns.

5. The method of claim 1 , wherein the step of forming an etch-resistant layer includes forming the etch-resistant layer of oxide or nitride.

6. The method of claim 1 , wherein the step of removing the etch-resistant layer includes removing the etch-resistant layer by wet etching.

7. The method of claim 1 , wherein the step of forming doped regions includes the steps of:

forming lightly doped regions in the substrate aligned with the pair of first and second gate patterns, respectively;

forming spacers on sidewalls of the pair of the first and second gate patterns, respectively; and

forming heavily doped regions in the substrate aligned with the spacers, respectively.

8. A method of fabricating a split gate flash memory device, comprising the steps of:

forming a first gate pattern covered with a cap layer on a semiconductor substrate in an active area;

forming an etchant-resistant layer covering one side of the first gate pattern, the etchant-resistant layer extending to a surface of the substrate to cover one confronting side of a neighboring first gate pattern in the active area;

forming an insulating layer on an exposed surface of the first gate pattern;

forming a second gate pattern covering the first gate pattern and the insulating layer, the second gate pattern not overlapping the etch-resistant layer;

removing the etch-resistant layer; and

forming a pair of doped regions in the substrate aligned with the first and second gate patterns.

9. The method of claim 8 , wherein the step of forming a first gate pattern with a cap layer includes forming the cap layer of an oxide layer and a nitride layer.

10. The method of claim 8 , wherein the step of forming a second gate pattern includes anisotropic etching a conductor layer deposited over the substrate including the etch-resistant layer and the first gate pattern.

11. The method of claim 8 , wherein the step of forming an etch-resistant layer includes forming the etch-resistant layer of oxide or nitride.

12. The method of claim 8 , wherein the step of removing an etch-resistant layer includes removing the etch-resistant layer by wet etch.

13. The method of claim 8 , wherein the step of forming doped regions includes the steps of:

forming lightly doped regions in the substrate aligned with the first and second gate patterns;

forming spacers on sidewalls of the first and second gates, respectively; and

forming heavily doped regions in the substrate aligned with the spacers, respectively.

14. A method of fabricating a split gate flash memory device comprising:

a step for forming a pair of first gate patterns on a semiconductor substrate in an active area a prescribed distance from each other;

a step for forming an etch-resistant layer pattern covering confronting sidewalls of the pair of first gate patterns and covering a surface of the substrate corresponding to the prescribed distance;

a step for forming an insulating layer on exposed surfaces of the pair of first gates;

a step for forming a pair of second gate patterns over the pair of first gate patterns, respectively, not overlapping the etch-resistant layer;

a step for removing the etch-resistant layer; and

a step for forming doped regions in the substrate aligned with the pair of first and second gate patterns, respectively.

15. The method of claim 14 , wherein the step for forming a pair of first gate patterns includes a step for forming a cap layer covering each of the pair of first gate patterns.

16. The method of claim 15 , wherein the step for forming a cap layer includes a step for forming the cap layer of an oxide layer and a nitride layer.

17. The method of claim 14 , wherein the step for forming a pair of second gate patterns includes a step for anisotropic etching a conductor layer deposited over the substrate including the etch-resistant layer and the first gate patterns.

18. The method of claim 14 , wherein the step for forming an etch-resistant layer includes a step for forming the etch-resistant layer of oxide or nitride.

19. The method of claim 14 , wherein the step for removing the etch-resistant layer includes a step for removing the etch-resistant layer by wet etching.

20. The method of claim 14 , wherein the step for forming doped regions includes:

a step for forming lightly doped regions in the substrate aligned with the pair of first and second gate patterns, respectively;

a step for forming spacers on sidewalls of the pair of the first and second gate patterns, respectively; and

a step for forming heavily doped regions in the substrate aligned with the spacers, respectively.