IP Library Granted Patent US 7,273,792
Granted Patent B2
US 7,273,792 · App. 11/024,742 · Granted Sep 25, 2007

Semiconductor device and fabricating method thereof

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Quick Facts
Patent No.
US 7,273,792
App. No.
11/024,742
Granted
Sep 25, 2007
Kind
B2
Abstract

A semiconductor device including a semiconductor substrate, a device isolation region formed by filling a trench in the semiconductor substrate with dielectric material and defining device regions in the semiconductor substrate. The trench has a rounded upper edge, and a dummy thin layer formed on the rounded upper edge.

Claims (22)

1. A method for fabricating a semiconductor device, comprising steps of:

depositing a first sacrificial oxide layer and a first sacrificial nitride layer on a semiconductor substrate;

exposing the substrate by selectively removing the first sacrificial nitride layer and the first sacrificial oxide layer through an etch process;

forming a trench within the substrate by removing the exposed substrate;

forming a device isolation region by filling the trench with dielectric material, the device isolation region defining first and second device regions;

depositing a second sacrificial nitride layer and a second sacrificial oxide layer on the substrate;

removing the second sacrificial oxide layer and the second sacrificial nitride layer on the first device region through a selective etch process; and

forming a dummy thin layer along an edge of the trench close to the first device region by performing a high temperature thermal treatment on the substrate.

2. The method of claim 1 , wherein the step of forming a dummy thin layer includes forming a rounded edge of the trench, wherein the rounded edge is adjacent to the first device region.

3. The method of claim 2 , wherein the step of forming a dummy thin layer includes forming the dummy thin layer to be rounded along the rounded edge of the trench.

4. The method of claim 1 , wherein the step of forming a dummy thin layer includes performing a high temperature thermal treatment at a temperature of 1000° C. or higher.

5. A method for fabricating a semiconductor device, comprising:

a step for depositing a first sacrificial oxide layer and a first sacrificial nitride layer on a semiconductor substrate;

a step for exposing the substrate by selectively removing the first sacrificial nitride layer and the first sacrificial oxide layer through an etch process;

a step for forming a trench within the substrate by removing the exposed substrate;

a step for forming a device isolation region by filling the trench with dielectric material, the device isolation region defining first and second device regions;

a step for depositing a second sacrificial nitride layer and a second sacrificial oxide layer on the substrate;

a step for removing the second sacrificial oxide layer and the second sacrificial nitride layer on the first device region through a selective etch process; and

a step for forming a dummy thin layer along an edge of the trench close to the first device region by performing a high temperature thermal treatment on the substrate.

6. The method of claim 5 , wherein the step for forming a dummy thin layer includes a step for forming a rounded edge of the trench, wherein the rounded edge is adjacent to the first device region.

7. The method of claim 6 , wherein the step for forming a dummy thin layer includes a step for forming the dummy thin layer to be rounded along the rounded edge of the trench.

8. The method of claim 5 , wherein the step for forming a dummy thin layer includes a step for performing a high temperature thermal treatment at a temperature of 1000° C. or higher.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041363/0572 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →