Methods of fabricating nonvolatile memory device
View Patent ↗A method of fabricating nonvolatile memory devices. The method includes forming a tunnel oxide layer, a stacked oxide layer, a polysilicon layer for a control gate, a buffer oxide layer and a buffer nitride layer in order on the entire surface of a semiconductor substrate, and patterning the substrate vertically to form a control gate and a first device isolation region. The method also includes implanting ions into the first device isolation region to form common source and drain regions, filling the gap of the first device isolation region to form a first device isolation structure, and removing the buffer nitride layer and the buffer oxide layer. The method further includes depositing polysilicon for a word line on the substrate, and patterning the substrate vertically to form the word line and a second device isolation region, forming sidewall spacers on the sidewalls of the control gate and the word line, and forming silicide on the word line.
1. A method of fabricating nonvolatile memories comprising the steps of:
forming a tunnel oxide layer, a stacked oxide layer, a polysilicon layer for a control gate, a buffer oxide layer and a buffer nitride layer in order on a surface of a semiconductor substrate;
patterning the semiconductor substrate vertically to form a control gate and a first device isolation region;
implanting ions into the first device isolation region to form common source and drain regions;
filling a gap of the first device isolation region to form a first device isolation structure;
removing a portion of the buffer nitride layer and a portion of the buffer oxide layer;
depositing polysilicon for a word line on the semiconductor substrate, and patterning the semiconductor substrate vertically to form the word line and a second device isolation region;
forming sidewall spacers on sidewalls of the control gate and the word line; and
forming silicide on the word line.
2. The method as defined by claim 1 , wherein the step of forming a stacked oxide layer includes forming the stacked oxide layer comprising a tunnel oxide layer, a storage oxide layer and a block oxide layer.
3. The method as defined by claim 2 , wherein the step of forming a tunnel oxide layer includes forming the tunnel oxide layer comprising a single layer or a multi-layer of a first tunnel oxide layer and a second tunnel oxide layer.
4. The method as defined by claim 3 , wherein the step of forming a tunnel oxide layer includes forming a single layer of one of SiO 2 , Al 2 O 3 and Y 2 O 3 with a thickness between about 30 Å and about 150 Å.
5. The method as defined by claim 3 , wherein the step of forming a tunnel oxide layer includes forming the first tunnel oxide layer of one of Al 2 O 3 , Y 2 O 3 , HfO 2 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3 and Lu 2 O 3 with a thickness between about 30 Å and about 150 Å, and forming the second tunnel oxide layer of one of SiO 2 , Al 2 O 3 and Y 2 O 3 with a thickness between about 5 Å and about 50 Å.
6. The method as defined by claim 2 , wherein the step of forming a stacked oxide layer includes forming the storage oxide layer of one of HfO 2 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3 and Lu 2 O 3 with a thickness between about 40 Å and about 500 Å.
7. The method as defined by claim 2 , wherein the step of forming a stacked oxide layer includes forming the block oxide layer comprising a single layer or a multi-layer of a first block oxide layer and a second block oxide layer.
8. The method as defined by claim 7 , wherein the step of forming a block oxide layer includes forming a single layer of one of SiO 2 , Al 2 O 3 and Y 2 O 3 with a thickness between about 40 Å and about 200 Å.
9. The method as defined by claim 7 , wherein the step of forming a block oxide layer includes forming the first block oxide layer of one of SiO 2 , Al 2 O 3 and Y 2 O 3 with a thickness between about 5 Å and about 50 Å, and forming the second block oxide layer of one of Al 2 O 3 , Y 2 O 3 , HfO 2 , ZrO 2 , BaZrO 2 , BaTiO 3 , Ta 2 O 5 , CaO, SrO, BaO, La 2 O 3 , Ce 2 O 3 , Pr 2 O 3 , Nd 2 O 3 , Pm 2 O 3 , Sm 2 O 3 , Eu 2 O 3 , Gd 2 O 3 , Tb 2 O 3 , Dy 2 O 3 , Ho 2 O 3 , Er 2 O 3 , Tm 2 O 3 , Yb 2 O 3 and Lu 2 O 3 with a thickness between about 40 Å and about 200 Å.
10. The method as defined by claim 1 , wherein the step of forming a polysilicon layer for a control gate includes forming the polysilicon layer with a thickness between about 500 Å and about 3000 Å.
11. The method as defined by claim 1 , wherein the step of forming a buffer oxide 30 layer includes forming the buffer oxide later with a thickness between about 100 Å and about 200 Å and the step of forming a buffer nitride layer includes forming the buffer nitride layer with a thickness between about 100 Å and about 2000 Å.
12. The method as defined by claim 1 , wherein the step of forming sidewall spacers on the sidewalls of the control gate and the word line includes simultaneously forming a second device isolation structure in the second device isolation region.
13. The method as defined by claim 1 , wherein the step of forming a second device isolation region includes etching the second device isolation structure more deeply than common source and drain regions to prevent a leakage current due to a punch-through between the common source and drain regions.
14. The method as defined by claim 1 , wherein the step of depositing polysilicon for a word line includes depositing polysilicon with a thickness between about 500 Å and about 3000 Å.