Method for fabricating a semiconductor device
View Patent ↗A semiconductor device including a semiconductor substrate having first and second device regions. A first trench is formed in the first region and a second trench is formed in the second region. The first trench and the second trench have different widths and different depths. The first trench and the second trench define device isolation regions and active regions.
1. A method for fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate having a high voltage region and a low voltage region;
forming wells to a depth selected to withstand high voltage in the high voltage region of the semiconductor substrate;
forming a first and a second trench for defining device isolation regions in the high voltage region and the low voltage region, respectively, of the semiconductor substrate;
forming a third trench to the depth of the wells by selectively etching a predetermined area of the substrate within the first trench formed in the high voltage region after forming the first trench, the third trench being formed deeper than the first trench; and
filling the first to the third trenches with a dielectric material.
2. The method of claim 1 , wherein the third trench is formed narrower than the first trench.
3. The method of claim 1 , wherein the third trench is formed deeper than the second trench.
4. The method of claim 1 , wherein the first and third trenches comprises a trench with stepped sidewalls.
5. The method of claim 1 , wherein the high voltage region comprises an NMOS transistor region and PMOS transistor region, and the first and third trenches are formed between the NMOS and PMOS transistor regions.
6. The method of claim 1 , wherein the high voltage region and the low voltage region are formed side-by-side on the substrate.
7. The method of claim 1 , further comprising the step of forming an oxide layer over the first and third trenches before the step of filling the first and third trenches with the dielectric material.
8. The method of claim 1 , wherein the first and third trenches are formed in the high voltage region and distal from the low voltage region.
9. The method of claim 1 , wherein the first and third trenches separate transistor source and drain regions.
10. The method of claim 1 wherein the third trench is formed to a depth which extends below the wells formed in the high voltage region.