IP Library Granted Patent US 7,290,227
Granted Patent B2
US 7,290,227 · App. 11/024,755 · Granted Oct 30, 2007

Method of calibrating semiconductor line width

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Quick Facts
Patent No.
US 7,290,227
App. No.
11/024,755
Granted
Oct 30, 2007
Kind
B2
Abstract

A method of calibrating a line width in a semiconductor device including fitting line width CD (critical dimension) data to a log function by measuring the line width CD data to plot selectively according to a space size in mask design, fabrication, and correction and applying an output value of the log function as a mask fabrication line width bias by selectively inputting a space value.

Claims (22)

1. A method of calibrating a semiconductor line width, comprising the steps of:

fitting line width CD (critical dimension) data to a log function by measuring the line width CD data to plot selectively according to a space size in mask design, fabrication, and correction; and

applying an output value of the log function as a mask fabrication line width bias, wherein the output value is obtained by inputting the space size to the log funtion;

wherein the step of fitting line width CD data includes fitting a gap between a DI (development image) CD bias and design CD and a gap between a FI (final image) CD bias and the design CD to an equation to facilitate bias correction between the DI CD and the FI CD.

2. The method of claim 1 , wherein the step of fitting line width CD data comprises the steps of:

generating an optimal model by correcting a design CD to measurement DI CD value of a prescribed line width with an optical model per pitch;

expressing a DI CD error and an FI CD error of isolated and dense lines per line width linearity;

plotting the FI CD error according to a space by comparing a CD error between the FI CD and the design CD based on a log function tendency of a CD of the dense line; and

fitting the CD data to the log function by numerical analysis using the plotted measurement data.

3. The method of claim 1 , wherein the step of applying an output value includes checking a bias correction value for a target CD by calculating an FI CD error value by inputting the space size to the log function.

4. The method of claim 1 , further comprising the step of expressing space sections with a divided log function if space sections cannot be fitted to one log function.

5. A method of calibrating a semiconductor line width comprising:

a step for fitting line width CD (critical dimension) data to a log function by measuring the line width CD data to plot selectively according to a space size in mask design, fabrication, and correction; and

a step for applying an output value of the log function as a mask fabrication line width bias, wherein the output value is obtained by inputting the space size;

wherein the step for fitting includes a step for fitting a gap between a DI (development image) CD bias and a design CD and a gap between a FI (final image) CD bias and the design CD to an equation to facilitate bias correction between the DI CD and the FI CD.

6. The method of claim 5 , wherein the step for fitting comprises:

a step for generating an optimal model by correcting a design CD to measurement DI CD value of a prescribed line width with an optical model per pitch;

a step for expressing a DI CD error and an FI CD error of isolated and dense lines per line width linearity;

a step for plotting the FI CD error according to a space by comparing a CD error between the FI CD and the design CD based on a log function tendency of a CD of the dense line; and

a step for fitting the CD data to the log function by numerical analysis using the plotted measurement data.

7. The method of claim 5 , wherein the step for applying an output value includes a step for checking a bias correction value for a target CD by calculating an FI CD error value by inputting the space size to the log function.

8. The method of claim 5 , further comprising a step for expressing space sections by a divided log function if space sections cannot be fitted to one log function.

Assignments (2)
CHANGE OF NAME Recorded May 23, 2006
From: DONGBU-ANAM SEMICONDUCTOR, INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017663/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2004
From: LEE, JUN SEOK
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 016136/0994 →