Method of fabricating MOS transistor
View Patent ↗A method of fabricating a CMOS (complementary metal oxide semiconductor) transistor includes manufacturing steps, by which adverse transistor characteristics can be prevented from being degraded by high-temperature annealing for hardening a screen oxide layer. The method includes steps of forming a gate on a semiconductor substrate with a gate oxide layer therebetween, forming a screen oxide layer on the substrate and the gate, forming a nitride layer on the screen oxide layer, forming LDD regions in the substrate substantially aligned with the gate, removing the nitride layer, forming a spacer on the screen oxide layer and on at least a portion of a sidewall of the gate, and forming in the substrate source/drain regions extending from the LDD regions respectively in the substrate substantially aligned with the spacer.
1. A method of fabricating a CMOS transistor, comprising the steps of:
forming a gate on a semiconductor substrate with a gate oxide layer therebetween;
forming a screen oxide layer on the substrate and the gate;
forming a nitride layer on the screen oxide layer; forming LDD regions in the substrate substantially aligned with the gate after forming the nitride layer;
forming a spacer on the screen oxide layer and on at least a portion of a sidewall of the gate, a sidewall portion including a oxide/nitride structure;
removing at least a portion of the nitride layer not on the sidewall;
forming in the substrate source/drain regions extending from the LDD regions respectively and substantially aligned with the spacer.
2. The method of claim 1 , wherein the method does not include a step of hardening the screen oxide layer by annealing.
3. The method of claim 1 , wherein the step of forming the nitride layer includes forming the nitride layer to have a thickness in an inclusive range of 5 Å. through 20 Å.
4. The method of claim 1 , wherein the step of forming the nitride layer includes forming by at least one of remote plasma nitridation and low pressure chemical vapor deposition.
5. The method of claim 1 , wherein the step of forming the gate comprises forming the gate with at least one material selected from the group consisting of polysilicon, tungsten, tungsten nitride, tungsten silicide, TiN, and Ti layers.
6. The method of claim 1 , further comprising the step of forming a silicide layer on the source/drain regions.
7. The method of claim 1 , wherein the step of forming a spacer includes forming the sidewall portion with a nitride/oxide/nitride structure.
8. A method of fabricating a CMOS transistor, comprising the steps of:
forming a gate on a semiconductor substrate with a gate oxide layer therebetween;
forming a screen oxide layer on the substrate and the gate;
forming a nitride layer on the screen oxide layer; forming LDD regions in the substrate substantially aligned with the gate after forming the nitride layer;
forming a spacer on the screen oxide layer and on at least a portion of a sidewall of the gate, a sidewall portion including a oxide/nitride structure;
removing at least a portion of the nitride layer not on the sidewall;
forming in the substrate source/drain regions extending from the LDD regions respectively and substantially aligned with the spacer.