Method of fabricating a fin transistor
View Patent ↗A method of fabricating a fin transistor is disclosed. An example method stacks a mask oxide layer and a nitride layer on a semiconductor substrate, forms a fin by etching the nitride and mask oxide layers and silicon, forms an insulating oxide layer, and forms a gate electrode by etching the insulating oxide layer corresponding to a gate forming area using a gate mask, by forming a gate oxide layer on a sidewall of the silicon exposed by the etch and burying a metal. The example method also removes the remaining insulating oxide layer using an etch rate difference, forms a gate spacer, and forms source/drain regions in the silicon substrate to be aligned with the gate electrode. Additionally, the example method forms a second insulating oxide layer over the substrate, etches the second insulating oxide layer using a metal mask, forms contact holes on the source/drain regions, respectively, and fills the contact holes and the portion etched via the metal mask with a metal.
1. A method of fabricating a fin transistor, comprising:
forming a silicon layer, a mask oxide layer and a nitride layer on a substrate;
forming a fin by etching the nitride and mask oxide layers and silicon layer;
forming a first insulating oxide layer;
etching the first insulating oxide layer corresponding to a gate forming area using a gate mask to expose the fin;
forming a gate oxide layer on a sidewall of the silicon layer exposed by the etch;
filling the etched portion of the first insulating oxide layer with a first metal to form a gate electrode;
removing the remaining first insulating oxide layer;
forming a gate spacer;
forming source/drain regions in the silicon layer aligned with the gate electrode;
forming a second insulating oxide layer over the substrate;
etching the second insulating oxide layer using a metal mask to form a trench exposing the gate electrode and to form trenches over the source/drain regions;
forming contact holes on the source/drain regions; and
filling the contact holes and the trenches with a second metal.
2. The method of claim 1 , wherein the substrate is an SOI substrate.
3. The method of claim 1 , wherein the gate mask is a contact hole type mask.
4. The method of claim 1 , wherein the first metal comprises W or Mo.
5. The method of claim 1 , wherein the width of the trenches is greater than the width of the contact holes.
6. The method of claim 1 , further comprising planarizing the second metal.
7. The method of claim 6 , wherein planarizing the second metal comprises a Chemical Mechanical Polishing (CMP) process.
8. The method of claim 1 , wherein the substrate comprises a first conductive type silicon substrate, a buried oxide layer on the first conductive type silicon substrate, and a polysilicon layer on the buried oxide layer.
9. The method of claim 1 , wherein forming the source/drain regions comprises high dose ion implantation.