IP Library Granted Patent US 7,030,790
Granted Patent B1
US 7,030,790 · App. 11/025,963 · Granted Apr 18, 2006

Systems and methods for auto gain control in Bi-CMOS digital to analog converters

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Quick Facts
Patent No.
US 7,030,790
App. No.
11/025,963
Granted
Apr 18, 2006
Kind
B1
Abstract

The accuracy of output power in a digital-to-analog converter (DAC) is critical in certain applications. When bi-CMOS technology is used to implement a DAC, a number of factors affect the gain accuracy of the DAC. The present invention provides a circuit architecture to reduce the variation in these factors to ensure the accuracy of the output power of a DAC. The architecture comprises a bandgap portion, replica circuit and a DAC. The bandgap portion of the architecture provides a constant voltage, while the replica circuit provide a correct current to drive the DAC.

Claims (19)

1. A digital to analog auto gain control system, comprising:

a constant voltage source;

a replica circuit coupled to said constant voltage source, wherein said replica circuit includes resistors and a beta compensation module having bipolar devices;

a digital-to-analog converter having bipolar devices coupled to said replica circuit, wherein said replica circuit provides a current to said digital-to-analog converter such that a voltage drop across said resistors tracks with a voltage of said constant voltage, wherein said beta compensation module compensates for a beta current loss in said digital-to-analog converter, wherein said beta compensation module bipolar devices mimic said digital-to-analog bipolar devices.

2. The digital-to-analog auto gain control system of claim 1 , wherein said replica circuit further comprises an operational amplifier that forces said current to said digital-to-analog converter such that a voltage drop across said resistors track with a voltage of said constant voltage.

3. The digital-to-analog auto gain control system of claim 1 , wherein said constant voltage source is provided by an external voltage reference.

4. The digital-to-analog auto gain control system of claim 1 , wherein said beta current compensation module comprises a transistor and current source.

5. The digital-to-analog auto gain control system of claim 1 , wherein said digital-to-analog auto gain control system compensates for potential performance degradation of said digital-to-analog converter attributable to manufacturing process variation of components of said digital-to-analog converter.

6. The digital-to-analog auto gain control system of claim 1 , wherein said digital-to-analog auto gain control system compensates for potential performance degradation of said digital-to-analog converter attributable to operating temperature variation.

7. A method for auto gain control in a digital-to-analog converter system having a digital-to-analog converter that includes bipolar devices and a beta compensation module that includes bipolar devices, comprising:

(a) receiving a digital code word;

(b) generating a constant current source based on a constant voltage source;

(c) reducing performance variations attributable to process variations, temperature changes and/or supply voltage variations;

(d) mimicking bipolar device operation within the digital to-analog converter with bipolar devices in the beta compensation module to compensate for beta current loss in the digital-to-analog converter; and

(e) outputting a converted analog signal based on the received digital code word.

8. The method of claim 7 , wherein said digital-to-analog converter is located on a chip with on-chip and off-chip resistors, wherein said reducing performance variations includes compensating for on-chip resistor variations and off-chip resistor variations.

9. The method of claim 8 , wherein the circuit layout of a differential pair includes more than one differential pair and multiple bipolar devices.

10. The method of claim 7 , wherein reducing performance variations includes supplying a constant voltage source.

11. The method of claim 7 , wherein reducing performance variations includes forcing a constant current source into the digital-to-analog converter.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2005
From: CHEN, CHUN-YING
To: BROADCOM CORPORATION
Reel/Frame 016141/0832 →