Semiconductor device and fabricating method thereof
View Patent ↗The present invention provides a semiconductor device and fabricating method thereof, by which capacitance is enhanced by increasing an effective area of a lower electrode of a capacitor. The present invention includes a first lower electrode on a semiconductor substrate to have a plate shape, a second lower electrode on the first electrode to have a type (or “wing”-type) cross-section, a dielectric layer covering surfaces of the first and second lower electrodes, and an upper electrode on the dielectric layer.
1. A method of fabricating a semiconductor device, comprising the steps of:
forming a first lower electrode on a substrate;
sequentially stacking a first sacrificial layer, a first metal layer, and a second sacrificial layer on the first lower electrode;
forming a trench by etching the second sacrificial layer, the first metal layer, and the first sacrificial layer to expose a central part of the first lower electrode;
forming a second metal layer over the substrate including the exposed central part of the first lower electrode and the second sacrificial layer;
patterning the second metal layer, the second sacrificial layer, the first metal layer, and the first sacrificial layer;
removing the remaining first and second sacrificial layers to expose a second lower electrode;
forming a dielectric layer covering surfaces of the first and second lower electrodes; and
forming an upper electrode on the dielectric layer.
2. The method of claim 1 , wherein the first and second sacrificial layers comprise an oxide.
3. The method of claim 1 , wherein removing the first and second sacrificial layers comprises wet etching the first and second sacrificial layers.
4. The method of claim 1 , wherein forming the dielectric layer comprises chemical vapor depositing the dielectric layer.
5. The method of claim 1 , wherein the upper electrode forming step comprises the steps of:
forming a third metal layer over the dielectric layer; and patterning the third metal layer and the dielectric layer.
6. The method of claim 5 , wherein forming the third metal layer comprises chemical vapor depositing the third metal layer.
7. The method of claim 1 , wherein patterning the second metal layer, the second sacrificial layer, the first metal layer, and the first sacrificial layer exposes a portion of the first lower electrode.
8. The method of claim 1 , wherein the second lower electrode has a wing shape after the remaining first and second sacrificial layers are removed.