Methods of forming silicide layer of semiconductor device

1. A method of forming silicide layers of a semiconductor device comprising:

sequentially depositing a polysilicon layer, a buffer oxide layer, and a buffer nitride layer on a semiconductor substrate;

forming a gate on the semiconductor substrate by removing some portion of the polysilicon layer, the buffer oxide layer, and the buffer nitride layer;

forming sidewall spacers on the sidewalls of the gate;

forming source and drain regions in the semiconductor substrate by performing an ion implantation process;

forming a first silicide layer on the source and drain regions;

depositing a first ILD layer over the semiconductor substrate including the gate and the first silicide layer;

removing some portion of the first ILD layer to expose the top surface of the gate;

forming a second silicide layer that covers the top of the gate and some portion of the sidewalls of the gate; and

depositing a second ILD layer over the semiconductor substrate including the second silicide layer and the first ILD layer.

2. A method as defined by claim 1 , wherein, following depositing the first ILD layer, the first ILD layer has a height equal to or less than that of the gate.

3. A method as defined by claim 1 , wherein removing some portion of the first ILD layer comprises an etch-back process.

4. A method as defined by claim 1 , wherein removing some portion of the first ILD layer is performed in consideration of the quantity of the silicide layer to be formed on the sidewalls of the gate by a later unit process.

5. A method as defined by claim 1 , further comprising removing the buffer oxide layer and the nitride layer on the gate after removing some portion of the first ILD layer.

6. A method as defined by claim 1 , wherein the second silicide layer formed on the gate has a thickness different from that of the first silicide layer formed on the source and drain regions.

7. A method as defined by claim 1 , wherein depositing the first ILD layer comprises high-density plasma chemical vapor deposition (HDP-CVD).

8. A method as defined by claim 1 , wherein depositing the first ILD layer comprises atmospheric pressure plasma chemical vapor deposition (APCVD).

9. A method as defined by claim 1 , wherein the first ILD layer comprises a boron phosphorus spin-on-glass.

10. A method as defined by claim 1 , wherein the first ILD layer comprises BPSG.

11. A method as defined by claim 1 , wherein the first ILD layer comprises phosphosilicate glass (PSG).

12. A method as defined by claim 1 , wherein removing the portion of the sidewall spacers comprises an etch-back process.

13. A method as defined by claim 1 , wherein removing the buffer oxide layer and the nitride layer comprises a wet etching process.

14. A method as defined by claim 1 , wherein removing the buffer oxide layer and the nitride layer comprises a dry etching process.

15. A method as defined by claim 3 , wherein further removing the first ILD layer and the sidewall spacers comprises a wet etching process.

16. A method as defined by claim 3 , wherein further removing the first ILD layer and the sidewall spacers comprises a dry etching process.

17. A method as defined by claim 1 , wherein the second ILD layer comprises boron phosphorus spin-on-glass.

18. A method as defined by claim 1 , wherein the second ILD layer comprises BPSG.

19. A method as defined by claim 1 , wherein the second ILD layer comprises phosphosilicate glass (PSG).

20. A method as defined by claim 1 , wherein removing some portion of the first ILD layer further exposes a portion of the sidewalls of the gate.