Granted Patent B2

US 7,238,606 · App. 11/026,941 · Granted Jul 3, 2007

Abstract

Claims (12)

1. A method for fabricating a copper interconnect of a semiconductor device comprising:

depositing a first insulating layer on a substrate having at least one predetermined structure;

forming a trench and a via hole through the first insulating layer by using a dual damascene process;

depositing a barrier layer along the bottom and the sidewalls of the trench and via hole;

forming a copper interconnect by filling the trench and via hole with copper and performing a planarization process, wherein filling the trench and via hole with copper is performed by using an electrochemical plating process;

depositing a Ta/TaN layer over the substrate including the copper interconnect;

removing some portion of the Ta/TaN layer so that the Ta/TaN layer remains only on the copper interconnect and the barrier layer by performing photolithography and etching processes;

depositing a second insulating layer over the substrate including the Ta/TaN layer;

forming a via hole through the second insulating layer by removing some portion of the second insulating layer; and

filling the via hole with a conductive material to complete a via.

2. A method as defined in claim 1 , wherein the barrier layer is made of Ta/TaN.

3. A method as defined by claim 1 , wherein the Ta/TaN layer on the copper interconnect is used as a capping layer.

Assignments (6)