Methods for preventing copper oxidation in a dual damascene process
View Patent ↗Methods of preventing oxidation of a copper interconnect of a semiconductor device are disclosed. An example method forms a lower copper interconnect on a substrate having at least one predetermined structure, deposits a nitride layer on the lower copper interconnect and on the substrate, and sequentially depositing a first insulating layer, an etch-stop layer, and a second insulating layer on the nitride layer. The example method also forms a trench and a via hole through the second insulating layer and the first insulating layer by using a dual damascene process, etches the nitride layer so as to expose some portion of the lower copper interconnect, and supplies combining gas onto the exposed portion of the lower copper interconnect.
1. A method for preventing oxidation of a copper interconnect of a semiconductor device, comprising:
forming a lower copper interconnect on a substrate having at least one predetermined structure;
depositing a nitride layer on the lower copper interconnect and on the substrate;
sequentially depositing a first insulating layer, an etch stop layer, and a second insulating layer on the nitride layer;
forming a trench and a via hole through the second insulating layer and the first insulating layer by using a dual damascene process;
etching the nitride layer so as to expose some portion of the lower copper interconnect; and
supplying combining gas onto the exposed portion of the lower copper interconnect, wherein the combining gas combines with the copper of the exposed portion of the lower copper interconnect,
wherein supplying the combining gas is carried out under conditions of time 20 sec/gap 30 mm/N 2 240 sccm/upper power 700 W/bottom power 70 W bottom temperature 20° C./cooling He edge 25 T/center 15 T at an error range of about 10%.
2. The method as defined by claim 1 , wherein the combining gas is nitrogen gas or hydrogen gas.
3. The method as defined by claim 2 , further comprising:
depositing a barrier metal layer on the first insulating layer, the second insulating layer, and the exposed portion of the lower copper interconnect;
forming a seed metal on the barrier metal layer; and
forming a via plug and upper copper interconnect on the seed metal.
4. The method as defined by claim 1 , further comprising:
depositing a barrier metal layer on the first insulating layer, the second insulating layer, and the exposed portion of the lower copper interconnect;
forming a seed metal on the barrier metal layer; and
forming a via plug and upper copper interconnect on the seed metal.
5. The method as defined by claim 1 , further comprising:
depositing a barrier metal layer on the first insulating layer, the second insulating layer, and the exposed portion of the lower copper interconnect;
forming a seed metal on the barrier metal layer; and
forming a via plug and upper copper interconnect on the seed metal.
6. A method for preventing oxidation of a copper interconnect of a semiconductor device, comprising:
forming a lower copper interconnect on a substrate having at least one predetermined structure;
depositing a nitride layer on the lower copper interconnect and on the substrate;
sequentially depositing a first insulating layer, an etch stop layer, and a second insulating layer on the nitride layer;
forming a trench and a via hole through the second insulating layer and the first insulating layer by using a dual damascene process;
etching the nitride layer so as to expose some portion of the lower copper interconnect; and
supplying combining gas onto the exposed portion of the lower copper interconnect, wherein the combining gas combines with the copper of the exposed portion of the lower copper interconnect,
wherein supplying the combining gas onto the exposed portion of the lower copper interconnect comprises having the combining gas present before some portion of the lower copper interconnect is exposed.
7. The method as defined by claim 6 , further comprising:
depositing a barrier metal layer on the first insulating layer, the second insulating layer, and the exposed portion of the lower copper interconnect;
forming a seed metal on the barrier metal layer; and
forming a via plug and upper copper interconnect on the seed metal.