Semiconductor devices and methods of manufacturing the same

1. A method of manufacturing a semiconductor device comprising;

forming an ion implant buffer film an a semiconductor substrate;

doping impurities to form an LDD region on the semiconductor substrate;

removing the ion implant buffer film;

growing a silicon layer by selective epitaxy;

doping ion impurities on the silicon layer to form a heavily doped layer;

forming a nitride film having a cutout wider than a gate forming region on the heavily doped layer;

etching the heavily doped layer using the nitride film as an etch mask to form source/drain regions;

forming a silicide preventing film on an upper surface of the LDD region and on sides of the source/drain regions;

forming lateral spacers within the cutout on lateral sides of the nitride film and on the silicide preventing film;

etching the silicide preventing film and the LDD region using the lateral spacers as an etch mask to expose a surface of the substrate;

forming a gate oxide layer on the exposed surface of the substrate;

forming a gate on the gate oxide layer;

removing the lateral spacers and the nitride film; and

forming silicide layers on the gate and the source/drain regions.

2. A method as defined in claim 1 , wherein forming the gate on the gate oxide layer further comprises:

forming a polysilicon layer on the substrate; and

etching the polysilicon layer to remove a portion of the polysilicon layer farmed outside of the gate forming region.

3. A method as defined in claim 1 , wherein the nitride film has a thickness of about 1000˜2000 Å.

4. A method as defined in claim 1 , wherein the silicon layer has a thickness of about 1000˜3000 Å.

5. A method as defined in claim 1 , wherein the gate oxide layer has a thickness of about 50˜200 Å and is formed by oxidation of the substrate.

6. A method as defined in claim 1 , further comprising:

after forming the suicide layers on the gate and the source/drain regions, fanning an interlayer insulating layer on the substrate, the interlayer insulating layer having contact holes exposing portions of the silicide layer; and

forming conductive plugs by filling the contact holes with conducting material.

7. A method as defined in claim 6 , wherein the conductive plugs are made of tungsten.

8. The method of claim 1 , wherein said step of forming a suicide preventing film comprises oxidizing the upper surface of the LDD region the sides of the source/drain regions using the nitride film as an oxidation hinder.

9. The method of claim 1 , wherein said step of forming lateral spacers comprises:

depositing a second nitride film in the cutout; and

etching the second nitride film to form the spacers.

10. The method of claim 1 , wherein said step of forming silicide layers comprises:

forming layers of metal atoms on the gate and the source/drain region; and

annealing the substrate.

11. A method of manufacturing a semiconductor device comprising;

forming an ion implant buffer film on a semiconductor substrate;

forming an LDD region by doping impurities in the semiconductor substrate;

removing the ion implant buffer film;

growing a silicon layer by selective epitaxy;

doping ion impurities on the silicon layer to form a heavily doped layer;

forming a nitride film having a cutout wider than a gate forming region on the heavily doped layer;

while using the nude film as an etch mask, etching the heavily doped layer to form source/drain regions;

forming spacers on the nitride film;

while using the spacers as an etch mask, etching the LDD region to expose a surface of the substrate;

forming a gate oxide layer on the exposed surface of the substrate;

forming a polysilicon layer to cover the nitride film on the gate oxide layer;

chemical mechanical polishing the polysilicon layer to form a gate;

forming an interlayer insulating layer on the gate;

forming contact holes in to interlayer insulating layer exposing portions of upper surfaces of the gate and the source/drain regions; and

filling the contact holes with conducting material to form conductive plugs.

12. A method as defined in claim 11 , wherein the chemical mechanical polishing of the polysilicon layer is performed until the nitride film is exposed and partially etched.

13. A method as defined in claim 11 , wherein the nitride film has a thickness of about 1000˜2000 Å.

14. A method as defined in claim 11 , wherein the silicon layer has a thickness of about 1000˜3000 Å.

15. A method as defined in claim 11 , wherein the gate oxide layer has a thickness of about 50˜200 Å and is formed by oxidation of the substrate.

16. A method as defined in claim 15 , wherein the conductive plugs are made of tungsten.

17. A method of manufacturing a semiconductor device comprising;

forming an LDD region on a semiconductor substrate;

growing a silicon layer on said LDD region by selective epitaxy;

doping ion impurities on the silicon layer to form a heavily doped layer;

forming a nitride film having a cutout wider than a gate forming region on the heavily doped layer;

etching the heavily doped layer using the nitride film as an etch mask to form source/drain regions; and

forming a gate in the gate forming region between the source/drain regions.

18. The method of claim 17 , wherein the step of forming a gate comprises:

forming a silicide preventing film on an upper surface of the LDD region and on sides of the source/drain regions;

forming spacers within the cutout on sidewalls of the nitride film and the silicide preventing film;

etching the silicide preventing film and the LDD region using the spacers as an etch mask to expose a surface of to substrate;

forming a gate oxide on the exposed surface of the substrate; and

forming the gate on the gate oxide layer.

19. The method of claim 18 , further comprising:

removing the spacers and the nitride film; and

forming silicide layers on the gate and the source/drain regions.

20. The method of claim 19 , wherein the step of forming the gate on the gate oxide layer further comprises:

forming a polysilicon layer on the substrate; and

etching the polysilicon layer to remove a portion of the polysilicon layer formed outside of the gate forming region.