Transistors and manufacturing methods thereof
View Patent ↗Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a channel region formed in the semiconductor substrate and overlapping the gate, and LDD regions formed in the semiconductor substrate and at both sides of the gate, centering the gate. In addition, the example transistor includes source and drain regions formed under the LDD regions, offset regions formed in the semiconductor substrate and between the channel region and LDD regions, and gate spacers formed at both sidewalls of the gate.
1. A transistor manufacturing process comprising:
(a) forming an ion-implanting buffer film on an active region of a semiconductor substrate;
(b) forming LDD regions in the semiconductor substrate by doping the substrate with impurity ions;
(c) forming a photoresist pattern wider than a gate formation region on the ion-implanting buffer film;
(d) removing the LDD regions partially using a mask of the photoresist film to expose the semiconductor substrate;
(e) forming offset regions at opposite sides of the LDD regions;
(f) forming a channel region on the exposed semiconductor substrate through a selective epitaxial growth process;
(g) forming a gate insulating film on the semiconductor substrate including the channel region;
(h) forming a gate on the gate insulating film, overlapping the channel region;
(i) forming gate spacers at both sidewalls of the gate; and
(j) forming source and drain regions by implanting conductive impurity ions with a mask of the gate spacers.
2. The transistor manufacturing process of claim 1 , wherein the offset regions are doped with P-type impurity ions when the LDD regions are doped with N-type impurity ions, and the offset regions are doped with N-type impurity ions when the LDD regions are doped with P-type impurity ions.
3. The transistor manufacturing process of claim 1 , wherein the transistor-forming operation (e) comprises depositing a doped poly film on an ion-implanting buffer film and back-etching the doped poly film.
4. The transistor manufacturing process of claim 3 , wherein the doped poly film has a thickness of 100 Å to 500 Å.
5. A transistor manufacturing process comprising:
(a) forming an ion-implanting buffer film on an active region of a semiconductor substrate;
(b) forming LDD regions in the semiconductor substrate by doping the substrate with impurity ions;
(c) forming a photoresist pattern wider than a gate formation region on the ion-implanting buffer film;
(d) partially removing the LDD regions using a mask of the photoresist film to expose the semiconductor substrate;
(e) forming offset regions at opposite sides of the LDD regions;
(f) forming a channel region on the exposed substrate through a selective epitaxial growth process;
(g) forming a gate insulating film on the semiconductor substrate including the offset regions;
(h) forming a gate on the gate insulating film;
(i) forming gate spacers at both sidewalls of the gate; and
(j) forming source and drain regions by implanting conductive impurity ions with a mask of the gate spacers.
6. The transistor manufacturing process of claim 5 , wherein the offset regions are doped with P-type impurity ions when the LDD regions are doped with N-type impurity ions, and the offset regions are doped with N-type impurity ions when the LDD regions are doped with P-type impurity ions.
7. The transistor manufacturing process of claim 5 , wherein the transistor forming operation (e) comprises depositing a doped poly film on an ion-implanting buffer film and back-etching the doped poly film.
8. The transistor manufacturing process of claim 6 , wherein the doped poly film has a thickness of 100 Å to 500 Å.