Silicide uniformity for lateral bipolar transistors
View Patent ↗Method and apparatus for forming a semiconductor device. The method includes defining a plurality of rows in a semiconductor layer. Thereafter, on one or more of the plurality of rows, one or more bipolar junction devices are formed. Each of the bipolar junction devices has a first end region and a second end region. A quantity of a pre-amorphization ion is then implanted into at least one of the first end region and the second end region of a bipolar junction device for example. A silicide is formed in the semiconductor layer at the first end region and the second end region having implanted therein the quantity of the pre-amorphization ion. Additionally, laterally extending upper edges of the plurality of rows forming corners may be rounded prior to the implantation of the pre-amorphization.
1. A semiconductor device comprising:
a plurality of rows defined in a semiconductor layer;
at least one bipolar junction device formed on at least one of the plurality of rows, the at least one bipolar junction device having a first end region and a second end region;
a quantity of a pre-amorphization ion implanted into at least one of the first end region and the second end region;
a silicide formed in the semiconductor layer along an upper surface thereof and to a finite depth therebelow in the at least one of the first end region and the second end region having implanted therein the quantity of the pre-amorphization ion;
at least one sidewall formed on at least one of the plurality of rows; and
a rounded corner formed along the at least one sidewall and the upper surface of the semiconductor layer.
2. The semiconductor device of claim 1 further comprising:
at least one gate conductive stripe formed substantially orthogonal to the plurality of rows; and
the semiconductor layer being annealed to provide source/drain dopant activation prior to the implantation of the quantity of the pre-amorphization ion into at the least one of the first end region and the second end region.
3. The semiconductor device of claim 2 wherein the at least one bipolar junction device comprises one of an npnp and a pnpn structure, and wherein the pre-amorphization ion is one of germanium and xenon.
4. The semiconductor device of claim 3 wherein the one of the npnp and the pnpn structure further is for thyristor-based memory device.
5. A semiconductor device comprising:
at least one row defined in a semiconductor layer, the at least one row defining at least one sidewall;
at least one top corner defined by a sidewall of the at least one row and an upper surface of the semiconductor layer, the top corner having a rounded profile;
at least one bipolar junction device formed in the at least one row;
a quantity of a pre-amorphization ion implanted into a portion of the semiconductor layer partially defined by the upper surface and the top corner; and
a silicide formed in the portion of the semiconductor layer and to a finite depth therebelow.
6. The semiconductor device of claim 5 wherein the at least one bipolar junction device comprises one of an npnp and a pnpn structure, and wherein the pre-amorphization ion is one of germanium and xenon.
7. The semiconductor device of claim 6 wherein the one of the npnp and the pnpn structure forms a thyristor-based memory device.
8. The semiconductor device of claim 7 further comprising:
at least one gate conductive stripe formed substantially orthogonal to the at least one row; and
the semiconductor layer being annealed to provide source/drain dopant activation prior to the implantation of the quantity of the pre-amorphization ion into the portion of the semiconductor layer partially defined by the upper surface and the top corner.