Method of forming plug of semiconductor device
View Patent ↗A method for forming a plug of a semiconductor device according to a preferred embodiment includes forming a metal wiring on a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate having the metal wiring, forming a contact hole for partially exposing the metal wiring by selectively etching the interlayer dielectric layer, annealing the semiconductor substrate having the contact hole using NH 3 gas, plasma processing the annealed semiconductor substrate using the NH 3 , and forming a barrier layer on the interlayer dielectric layer having the contact hole.
1. A method for forming a plug in a semiconductor device comprising:
annealing a semiconductor substrate in a chamber in an environment containing NH 3 gas, the semiconductor substrate having thereon a metal wiring, an interlayer dielectric layer on or over the metal wiring, and a contact hole in the interlayer dielectric layer partially exposing the metal wiring;
plasma processing the annealed semiconductor substrate including the contact hole in the interlayer dielectric layer and the exposed metal wiring in-situ in the chamber in the presence of NH 3 sufficiently to remove a polymer on the exposed metal wiring; and
forming a barrier layer on the interlayer dielectric layer and in the plasma processed contact hole in-situ in the chamber.
2. The method of claim 1 , wherein the metal wiring comprises copper.
3. The method of claim 1 , further comprising:
depositing a conductive layer on the barrier layer to fill the contact hole;
annealing the conductive layer; and
chemical mechanical polishing the conductive layer and the barrier layer until an upper surface of the interlayer dielectric layer is exposed.
4. The method of claim 1 , wherein the annealing and plasma processing are carried out at a pressure in the range of from 5 to about 70 Torr.
5. The method of claim 1 , wherein the semiconductor substrate is annealed sufficiently to reduce a native oxide.
6. The method of claim 1 , wherein forming the barrier layer comprises plasma depositing the barrier layer.
7. The method of claim 1 , wherein the annealing and plasma processing are carried out at a temperature in the range of from 150 to about 500° C.
8. The method claim 7 , wherein the annealing and plasma processing are carried out at a pressure in the range of from 5 to about 70 Torr.
9. The method of claim 1 , further comprising forming the metal wiring on the semiconductor substrate.
10. The method of claim 9 , further comprising forming the interlayer dielectric layer on or over the metal wiring.
11. The method of claim 10 , further comprising selectively etching the interlayer dielectric layer to form the contact hole.
12. The method of claim 11 , wherein the annealing and plasma processing are carried out at a temperature in the range of from 150 to about 500° C.
13. A method for forming a plug in a semiconductor device comprising:
annealing a semiconductor substrate in a chamber in an environment containing NH 3 gas or N 2 H 4 the semiconductor substrate having thereon a metal wiring, an interlayer dielectric layer on or over the metal wiring, and a contact hole in the interlayer dielectric layer partially exposing the metal wiring;
plasma processing the annealed semiconductor substrate including the contact hole in the interlayer dielectric layer and the exposed metal wiring in-situ in the chamber in the presence of said NH 3 gas or N 2 H 4 sufficiently to remove a polymer on the exposed metal wiring; and
forming a barrier layer on the interlayer dielectric layer and in the plasma processed contact hole in-situ in the chamber.
14. The method of claim 13 , wherein the environment contains NH 3 gas.
15. The method of claim 13 , wherein the environment contains N 2 H 4 .
16. The method of claim 13 wherein the metal wiring comprises copper.
17. The method of claim 13 further comprising:
depositing a conductive layer on the barrier layer to fill contact hole;
annealing the conductive layer; and
chemical mechanical polishing the conductive layer and the barrier layer until an upper surface of the interlayer dielectric layer is exposed.
18. The method of claim 13 , wherein the annealing and plasma processing are carried out at a temperature in the range of from 150 to about 500°C.
19. The method of claim 13 , wherein the annealing and plasma processing are carried out at a pressure in the range of from 5 to about 70 Torr.
20. The method of claim 13 , further comprising forming the metal wiring on the semiconductor substrate, forming the interlayer dielectric layer on or over the metal wiring, and selectively etching the interlayer dielectric layer to form the contact hole.
21. The method of claim 13 wherein the semiconductor substrate is annealed sufficiently to reduce a native oxide.
22. The method of claim 13 , wherein forming the barrier layer comprises plasma depositing the barrier layer.