Methods of fabricating via hole and trench
View Patent ↗A method of fabricating a via and a trench is disclosed. A disclosed method comprises: forming a via hole and a trench in a interlayer dielectric layer on a semiconductor substrate where a predetermined device is formed; depositing a thin Hf layer on the substrate; performing a thermal treatment of the substrate to getter oxygen and forming a barrier layer; and filling copper into the via hole and the trench.
1. A method comprising:
forming an interlayer dielectric layer over a lower copper interconnect on a semiconductor substrate where a predetermined device is formed;
forming a via hole and a trench in said interlayer dielectric layer to expose the lower copper interconnect to air;
depositing a thin Hf layer on said exposed lower copper interconnect;
performing a thermal treatment of the substrate to getter oxygen, and forming a barrier layer over the substrate; and
filling copper into the via hole and the trench.
2. The method as defined by claim 1 , wherein the thin Hf layer has a thickness between 50 Å and 500 Å.
3. The method as defined by claim 1 , wherein the thermal treatment reduces copper oxide on the lower copper interconnect to form a Cu/Hf interface.
4. The method as defined by claim 1 , wherein the thermal treatment comprises an RTP or a furnace thermal treatment and the barrier layer comprises Ti, TiN, Ta, TaN, WN x or their combination.
5. The method as defined by claim 1 , wherein the thermal treatment comprises an RTP or a furnace thermal treatment to build up a HfN x layer as the barrier layer on the thin Hf layer.
6. The method as defined by claim 1 , wherein forming the barrier layer comprises depositing a HfN x layer on the thin Hf layer in-situ in high vacuum by a PVD process or a CVD process, or ex-situ in another chamber or equipment before performing the thermal treatment.
7. The method as defined by claim 1 , wherein depositing the thin Hf layer comprises an ionized PVD that provides some energy for reducing copper oxide formed by exposing the lower copper interconnect to air, thereby generating a Hf/Cu interface.
8. The method as defined by claim 1 , further comprising carrying out a preclean RF etch process using Ar + ions before depositing the thin Hf layer on the substrate.
9. The method as defined by claim 8 , wherein the preclean RF etch is carried out to the extent that the interlayer dielectric layer is etched with a thickness between 10 Å and 100 Å.
10. The method as defined by claim 1 , wherein the via hole and trench are formed by performing a dual damascene process in the interlayer dielectric layer.
11. The method as defined by claim 10 , wherein exposing the lower copper interconnect to the air forms copper oxide or a copper oxide layer.
12. The method as defined by claim 1 , wherein said thin Hf layer serves as a reductant of copper oxide.
13. The method as defined by claim 12 , wherein said thin Hf layer is deposited by a physical vapor deposition process.
14. The method as defined by claim 12 , wherein said thin Hf layer is deposited by a chemical vapor deposition process.
15. The method as defined by claim 1 , further comprising carrying out a planarization process after filing copper into the via hole and the trench.
16. The method as defined by claim 1 , wherein forming the barrier layer comprises depositing a HfN x layer on the thin Hf layer.
17. The method as defined by claim 16 , wherein the HfN x layer is deposited in-situ by a PVD process before performing the thermal treatment.
18. The method as defined by claim 16 , wherein the HfN x layer is deposited ex-situ by a CVD process in another chamber or equipment before performing the thermal treatment.