Methods of fabricating semiconductor devices
View Patent ↗Methods of fabricating CMOS transistors are disclosed. A disclosed method includes forming first and second gate patterns on the first and second wells, respectively; forming a sidewall insulating layer over the substrate; forming first lightly doped regions in the first well by NMOS LDD ion implantation; forming a first gate spacer insulating layer over the substrate; forming second lightly doped regions in the second well by PMOS LDD ion implantation; sequentially stacking a spacer insulating layer and a second gate spacer insulating layer on the first gate spacer insulating layer; forming first and second spacers on sidewalls of the first and second gate patterns; and forming first and second heavily doped regions in the first and second wells by NMOS and PMOS source/drain ion implantations, respectively.
1. A method of fabricating CMOS transistors comprising:
forming a first well and a second well in active areas of a semiconductor substrate;
forming first and second gate patterns on gate insulating layers on the first and second wells, respectively;
forming a sidewall insulating layer;
performing NMOS LIDD ion implantation to form first lightly doped regions in the first well;
forming a first gate spacer insulating layer over the sidewall insulating layer;
performing PMOS LDD ion implantation to form second lightly doped regions in the second well;
sequentially stacking a spacer insulating layer and a second gate spacer insulating layer on the first gate spacer insulating layer;
patterning the second and first gate spacer insulating layers and the sidewall insulating layer to form first and second spacers on sidewalls of the first and second gate patterns and expose upper surfaces of the semiconductor substrate in areas of the first and second lightly doped regions;
performing NMOS source/drain ion implantation to form first heavily doped regions in the first well; and
performing PMOS source/drain ion implantation to form second heavily doped regions in the second well.
2. A method as defined in claim 1 , wherein the second lightly doped regions and the second heavily doped regions we doped with BF 1 and/or BF 2 ions.
3. A method as defined in claim 1 , wherein the PMOS LDD ion implantation is performed at about 10˜50 KeV.
4. A method as defined in claim 3 , wherein the second lightly doped regions have a deep junction profile.
5. A method as defined in claim 1 , further comprising forming device isolation layers in the semiconductor substrate to define the active areas.
6. A method as defined in claim 5 , wherein the device isolation layers are formed prior to forming the first and second wells and are disposed between the first and second wells.
7. A method as defined in claim 1 , wherein the gate insulating layers comprise an oxide layer.
8. A method as defined in claim 1 , wherein forming the first and second gate patterns comprises depositing and patterning a polysilicon layer.
9. A method as defined in claim 1 , wherein forming the sidewall insulating layer comprises forming an oxide layer over The semiconductor substrate including the first and second gate patterns.
10. A method as defined in claim 9 , wherein the sidewall insulating layer has a thickness of about 20˜50 Å.
11. A method as defined in claim 1 , wherein the first and second lightly doped regions are aligned with the first and second gate patterns, respectively.
12. A method as defined in claim 1 , wherein the spacer insulating layer comprises a nitride layer having a thickness of about 500˜700 Å.
13. A method as defined in claim 1 , wherein the second gate spacer insulating layer comprises an oxide layer and has a thickness of about 100˜300 Å.
14. A method as defined in claim 1 , wherein patterning the second and first gate spacer insulating layers and the sidewall insulating layer to form first and second spacers comprises anisotropically etching the second and first gate spacer insulating layers and the sidewall insulating layer.
15. A method as defined in claim 1 , wherein the first and second heavily doped regions are aligned with the first and second spacers, respectively.
16. A method as defined in claim 1 , further comprising annealing the semiconductor substrate after forming the second heavily doped regions.
17. A method of fabricating CMOS transistors comprising:
forming a first well and a second well in active areas of a semiconductor substrate;
forming first and second gate patterns on gate insulating layers on the first and second wells, respectively;
forming a sidewall insulating layer over the first and second gate patterns;
forming a first gate spacer insulating layer over the sidewall insulating layer;
performing NMOS LDD ion implantation to form first lightly doped regions in the first well alter forming the first gate spacer insulating layer;
performing PMOS LDD ion implantation to form second lightly doped regions in the second well;
sequentially stacking a spacer insulating layer and a second gate spacer insulating layer on the first gate spacer insulating layer;
patterning the first and second gate spacer insulating layers and the sidewall insulating layer to form first and second spacers on sidewalls of the first and second gate patterns, respectively, and expose upper surfaces of the semiconductor substrate in areas of the first and second lightly doped regions; and
performing NMOS source/drain ion implantation to form first heavily doped regions in the first well of the substrate; and
performing PMOS source/drain ion implantation to form second heavily doped regions in the second well of the substrate.
18. A method as defined in claim 17 , wherein the second lightly doped regions and the second heavily doped regions are doped with BF 1 and/or BF 2 ions.
19. A method as defined in claim 17 , wherein the PMOS LDD ion implantation is performed at about 10˜50 KeV.
20. A method of fabricating CMOS transistors comprising:
forming a first well and a second well in active areas of a semiconductor substrate;
forming first and second gate patterns on gate insulating layers on the first and second wells, respectively;
forming a sidewall insulating layer;
performing NMOS LDD ion implantation to form first lightly doped regions in the first well;
forming a first gate spacer insulating layer over the sidewall insulating layer;
performing PMOS LDD ion implantation to form second lightly doped regions in the second well;
sequentially stacking a spacer insulating layer and a second gate spacer insulating layer comprising an oxide layer having a thickness of about 100˜300 Å on the first gate spacer insulating layer;
patterning the second and first gate spacer insulating layers and the sidewall insulating layer to form first and second spacers on sidewalls of the first and second gate patterns;
performing NMOS source/drain ion implantation to form first heavily doped regions in the first well; and
performing PMOS source/drain ion implantation to form second heavily doped regions in the second well.