IP Library Patent Application 11027517
Patent Application
App. No. 11/027,517

Methods of fabricating metal lines in semiconductor devices

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Quick Facts
Patent No.
US None
App. No.
11/027,517
Abstract

Methods to form metal lines in semiconductor devices are disclosed. An illustrated method comprises: depositing first and second interlayer dielectric layers on a semiconductor substrate; forming a via hole in the second interlayer dielectric; forming a photoresist pattern, forming a trench, using the photoresist pattern as a mask; removing an portion of the first interlayer dielectric layer that is exposed through the trench; and filling metal in the via hole and the trench to form the metal line. Etching the second interlayer dielectric layer, removing the photoresist pattern; and removing the exposed portion of the first interlayer dielectric layer are performed in-situ in the same chamber.

Claims (11)

1 . A method for forming a metal line in a semiconductor device comprising:

depositing first and second interlayer dielectric layers on a semiconductor substrate;

forming a via hole in the second interlayer dielectric;

forming a photoresist pattern;

etching the second interlayer dielectric layer while using the photoresist pattern as a mask to form a trench;

removing the photoresist pattern;

removing a portion of the first interlayer dielectric layer exposed through the trench; and

filling metal in the via hole and the trench to form the metal line, wherein etching the second interlayer dielectric layer, removing the photoresist pattern; and removing the exposed portion of the first interlayer dielectric layer are performed in-situ in a chamber.

2 . A method as defined in claim 1 , wherein etching the second interlayer dielectric layer is performed with a chamber pressure at about 120˜180 mT, RF power connected to a first electrode within the chamber at about 320˜480 W at a frequency of about 1.6˜2.4 MHz, RF power connected to a second electrode within the chamber at about 320˜480 W at a frequency of about 21.6˜28.4 MHz, and while introducing Ar at about 160˜240 sccm, CF 4 at about 40˜60 sccm, O 2 at about 7.2˜10.8 sccm and CHF 3 at about 20˜30 sccm at a temperature of about 16° C. to about 24° C. for about 40˜60 seconds.

3 . A method as defined in claim 1 , wherein removing the photoresist pattern is performed with a chamber pressure of about 248˜372 mT, RF power connected to a first electrode within the chamber at about −20˜20 W at a frequency of about 1.6˜2.4 MHz, RF power connected to a second electrode within the chamber at about 340˜360 W at a frequency of about 21.6˜28.4 MHz, and while introducing O 2 at about 1,520˜2,280 sccm at a temperature of about 16° C. to about 24° C. for about 40˜80 seconds.

4 . A method as defined in claim 1 , wherein removing the portion of the first interlayer dielectric is performed with a chamber pressure of about 80˜120 mT, RF power connected to a first electrode within the chamber at about 80˜120 W at a frequency of about 1.6˜2.4 MHz, RF power connected to the second electrode within the chamber at about 340˜360 W at a frequency of about 21.6˜28.4 MHz, and while introducing Ar at about 360˜540 sccm, CF 4 at about 5.6˜8.4 sccm, CHF 3 at about 11.2˜16.8 sccm and O 2 at about 6.4˜9.6 sccm at a temperature ranging from about 16° C. to about 24° C. for about 24˜36 seconds.

Assignments (2)
CHANGE OF NAME Recorded Sep 7, 2007
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 019800/0147 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2004
From: NAM, SANG WOO
To: DONGBUANAM SEMICONDUCTOR, INC.
Reel/Frame 016151/0426 →