Methods for forming copper interconnect of semiconductor devices
View Patent ↗Methods for forming a copper interconnect of a semiconductor device are disclosed. A disclosed method comprises forming a lower metal interconnect; sequentially depositing a capping layer, a first insulating layer, and a second insulating layer on the lower metal interconnect; forming a via hole by etching the first insulating layer and the second insulating layer; forming a trench and terraces by etching the second insulating layer; and exposing at least a portion of the top surface of the lower metal interconnect by etching the capping layer.
1. A method for forming a copper interconnect for a semiconductor device comprising:
forming a lower metal interconnect;
sequentially depositing a capping layer, a first insulating layer, and a second insulating layer over the lower metal interconnect, wherein the second insulating layer is deposited on the first insulating layer directly after depositing the first insulating layer, and wherein the second insulating layer is neither an antireflecting layer nor an etch stop layer;
etching the first insulating layer and the second insulating layer to form a via hole;
etching the second insulating layer to form a trench;
forming terraces by removing edge portions of the upper part of the via hole; and
etching the capping layer to expose at least a portion of a top surface of the lower metal interconnect.
2. The method as defined by claim 1 , wherein the capping layer comprises silicon nitride and has a thickness between about 200 Å and about 400 Å.
3. The method as defined by claim 1 , wherein the first insulating layer comprises fluorinated silica glass (FSG) having a low dielectric constant and a thickness between about 7000 Å and about 10000 Å.
4. The method as defined by claim 1 , wherein the second insulating layer comprises phospho-silicate glass (PSG).
5. The method as defined by claim 1 , wherein etching the second insulating layer to form the trench and forming the terraces are performed by an etching apparatus using a dual plasma source.
6. The method as defined by claim 5 , wherein the etching apparatus is operated with a source power between about 1000 W and about 1500 W, a bias power between about 500 W and about 1000 W, an etching chamber internal pressure between about 20 mTorr and about 100 mTorr, and an etching chamber volume between about 30 L and about 45 L.
7. The method as defined by claim 5 , wherein etching the second insulating layer to form the trench comprises using CHF 3 at a rate between about 20 sccm and about 50 sccm, CF 4 at a rate between about 50 sccm and about 100 sccm, Ar at a rate between about 100 sccm and 400 sccm, and O 2 at a rate between about 5 sccm and 15 sccm, as etching gases.
8. The method as defined by claim 1 , wherein at least one of the terraces has an inclined plane oriented at an angle between about 60° and about 80° from a contact surface between the trench and the via hole, wherein the contact surface is perpendicular to a top surface of the first insulating layer.
9. The method as defined by claim 1 , wherein etching the capping layer is performed by an etching apparatus using a dual plasma source.
10. The method as defined by claim 9 , wherein the etching apparatus is operated with a source power between about 1500 W and about 2000 W, a bias power between about 1000 W and about 1500 W, an etching chamber internal pressure between about 20 mTorr and about 40 mTorr, and an etching chamber volume between about 20 L and about 30 L.
11. The method as defined by claim 9 , wherein etching the capping layer comprises using CHF 3 at a rate between about 20 sccm and about 30 sccm, CF 4 at a rate between about 10 sccm and about 200 sccm, and Ar at a rate between about 200 sccm and 300 sccm, as etching gases.
12. The method as defined by claim 1 , further comprising depositing a bottom antireflection coating to fill the via hole after etching the first insulating layer and the second insulating layer to form the via hole.
13. The method as defined by claim 12 , further comprising selectively removing a portion of the bottom antireflection coating after forming the terraces.
14. The method as defined by claim 1 , wherein the trench has a depth between about 3000 Å and about 5000 Å.
15. The method as defined by claim 1 , wherein the trench has a depth having a uniformity of about 30%.
16. The method as defined by claim 1 , wherein etching the capping layer is performed without an etch-stop layer, and wherein etching the capping layer removes an exposed portion of the terraces to form complete terrace structure.
17. The method as defined by claim 1 , wherein etching the capping layer forms an inclined plane for the terraces of an angle between about 60° and about 70° from a contact surface between the trench and the via hole, wherein the contact surface is perpendicular to a top surface of the first insulating layer.
18. The method as defined by claim 1 , wherein an etching selectivity of the capping layer to the first and second insulating layers is less than 1 to 0.7.