Method of fabricating MIM capacitor

1. A method of fabricating a MIM capacitor, comprising the steps of:

patterning a first metal layer on a first insulating layer on a substrate;

forming a planarized second insulating layer having a trench exposing a first portion of the patterned first metal layer therein;

forming a second metal layer within the trench;

forming a first dielectric layer on the second metal layer;

forming first via holes exposing second portions of the patterned first metal layer;

forming first plugs filling the trench and the first via holes;

forming a third metal layer over the first plugs in the trench and the first via holes;

forming a second dielectric layer on the third metal layer;

forming a patterned fourth metal layer on the second dielectric layer;

patterning the second dielectric layer and the third metal layer;

forming a planarized third insulating layer having second via holes therein over the third and fourth metal layers; and

forming a patterned fifth metal layer on the third insulating layer including the second via holes.

2. The method of claim 1 , wherein the first dielectric layer comprises SiO 2 , a silicon oxynitride (SiON), or silicon nitride (SiN).

3. The method of claim 1 , wherein the first dielectric layer is from about 500 to about 1,000 Å thick.

4. The method of claim 1 , wherein each of the third and fifth metal layers comprises a Ti/TiN/Al_Cu/Ti/TiN multi-layer.

5. The method of claim 1 , wherein the second dielectric layer is from about 500 to about 1,000 Å thick.

6. The method of claim 1 , wherein the second dielectric layer comprises SiO 2 , a silicon oxynitride (SiON), or silicon nitride (SiN).

7. The method of claim 1 , wherein the fourth metal layer comprises a Ti/TiN multi-layer about 1,500 to about 2,000 Å thick.

8. The method of claim 1 , wherein the first metal layer forms at least part of a lower capacitor electrode.

9. The method of claim 1 , wherein the patterned fourth metal layer forms at least part of an intermediate capacitor electrode.

10. The method of claim 1 , wherein the fifth metal layer forms an upper capacitor electrode.

11. A MIM capacitor, comprising:

a first metal layer on a first insulating layer on a substrate;

a planarized second insulating layer having a trench over a first portion of the first metal layer;

a second metal layer in the trench;

a first dielectric layer on the second metal layer;

first vias over second portions of the first metal layer;

first plugs in the trench and the first vias;

a third metal layer over the first plugs, the first plugs bring in the trench and the first vias;

a second dielectric layer on the third metal layer;

a fourth metal layer on the second dielectric layer;

a planarized third insulating layer having second vias therein over the third and fourth metal layers; and

a fifth metal layer on the third insulating layer and the second via holes.

12. The MIM capacitor of claim 11 , wherein the first dielectric layer comprises SiO 2 , a silicon oxynitride (SiON), or silicon nitride (SiN).

13. The MIM capacitor of claim 11 , wherein the first dielectric layer is from about 500 to about 1,000 Å thick.

14. The MIM capacitor of claim 11 , wherein each of the third and fifth metal layers comprises an Al_Cu alloy.

15. The MIM capacitor of claim 11 , wherein the second dielectric layer is from about 500 to about 1,000 Å thick.

16. The MIM capacitor of claim 11 , wherein the second dielectric layer comprises SiO 2 , a silicon oxynitride (SiON), or silicon nitride (SiN).

17. The MIM capacitor of claim 11 , wherein the fourth metal layer comprises a Ti/TiN multi-layer about 1,500 to about 2,000 Å thick.

18. The MIM capacitor of claim 11 , wherein the first metal layer forms at least part of a lower capacitor electrode.

19. The MIM capacitor of claim 11 , wherein the fourth metal layer forms at least part of an intermediate capacitor electrode.

20. The MIM capacitor of claim 11 , wherein the fifth metal layer forms an upper capacitor electrode.