Method for fabricating semiconductor device
View Patent ↗A method of fabricating a semiconductor device is provided, by which oxide on a Cu surface after via-etch can be removed using Hf (hafnium) as a barrier material. The method includes the steps of forming a Cu line in at least one protective insulating layer on a substrate, forming a via hole in the protective insulating layer to expose a portion of the Cu line, forming an Hf-containing layer in the via hole to cover the exposed portion of the embedded Cu line, and forming a conductive layer over the Hf-containing layer.
1. A method of fabricating a semiconductor device, comprising the steps of:
forming at least one protective insulating layer on a Cu line in a substrate;
forming a via hole in the at least one protective insulating layer to expose a portion of the Cu line;
forming a layer comprising Hf in the via hole to cover the exposed portion of the Cu line; and
forming a conductive layer comprising an HfNx layer over the substrate, on the Hf-containing layer.
2. The method of claim 1 , wherein the Hf-containing layer has a thickness of from about 50 to about 500 Å.
3. The method of claim 1 , wherein the step of forming the Hf-containing layer comprises ionized physical vapor depositing Hf or an Hf precursor.
4. The method of claim 1 , wherein an oxide layer on the exposed portion of the embedded Cu line is reduced by the Hf-containing layer.
5. The method of claim 1 , wherein the HfNx layer-forming step comprises rapid thermal annealing or furnace annealing.
6. The method of claim 1 , further comprising the step of performing RF etch pre-cleaning using Ar+ ions before forming the Hf-containing layer.
7. The method of claim 6 , wherein the RF etch pre-cleaning removes a thickness of from about 10 to abut 100 Å of the at least one protective insulating layer.
8. The method of claim 1 , wherein the conductive layer forming step further comprises a step of forming a tungsten plug on the HfNx layer in the via hole.
9. The method of claim 8 , wherein the conductive layer forming step further comprises a step of:
depositing Al over the substrate including the tungsten plug.
10. A metallization structure for a semiconductor device, comprising:
a Cu line in a substrate;
at least one protective insulating layer having a via hole therein to expose a portion of the Cu line;
a layer comprising Hf in the via hole to cover the exposed portion of the Cu line; and
a conductive layer comprising an HfNx barrier layer on the Hf-containing layer.
11. The metallization structure of claim 10 , wherein the Hf-containing layer has a thickness of from about 50 to about 500 Å.
12. The metallization structure of claim 10 , wherein the conductive layer further comprises Al and/or Cu.
13. The metallization structure of claim 10 , wherein the conductive layer further comprises Cu.
14. The metallization structure of claim 10 , wherein the conductive layer further comprises Al.
15. The metallization structure of claim 14 , wherein the conductive layer further comprises a tungsten plug between the Al and the HfNx barrier layer.